Minimum leakage pattern generation using stack effect

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn 2, Issue , 2003, Pages 1239-1242

  Xu, Yongjun ^a,c   Luo, Zuying ^b   Chen, Zhiguo ^a,d   Li, Xiaowei ^a,c  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

^b TSINGHUA UNIVERSITY   (China)

^c UNIVERSITY OF CHINESE ACADEMY OF SCIENCES   (China)

^d UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

Author keywords

Leakage power; MLP; Stack effect

Indexed keywords

SPICE;

AREA OVERHEAD; CIRCUIT SIMULATORS; HIGH-PERFORMANCE CIRCUITS; INPUT VECTOR CONTROL; LEAKAGE POWER; PATTERN GENERATION; STANDBY MODE; VLSI INDUSTRY;

LEAKAGE CURRENTS;

EID: 79957562480     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2003.1277439     Document Type: Conference Paper

References (17)

1. Kaushik Roy, Sharat Prasad. " Low Power CMOS VLSI Circuit Design [M]", New York: A Wiley Interscience Publication, 2000.
2. R. X. Gu and M. I. Elmasry, "Power Dissipation Analysis and Optimization of Deep Submcron CMOS Digital Circuits"[J], IEEE Journal on Solid State Circuits, vol. 31, No. 5, May 1996. P8S7-S93.
3. Jams Kao, Siva Narendra and Anantha Chandrakasan, " Subthreshold Leakage Modeling and Reduction Techniques", In Proceeding of ICCAD2002, San Jose, CA, November 1044, 2002. P28-34.
4. Vivek De, " Leakage-tolerant design techniques for high performance processors (Invited paper)"[J], Proceedings of 2002 International Symposium on Physical Design, April 7-10, 2002,. San Diego, California, USA. P28.
5. Mark C.Johnson, Dinesh Somasekhar, Lih-Yih Chiou Kaushik Roy, " Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS"[J], IEEE transactions on VLSI Systems, Vol.10, No. 1 February 2002. Pl-5.
6. Qi Wang, Sarna E. K Vrudhula, " Algorithms for Minimizing Standby Power in Deep Submicrometer, Dual-Vt CMOS Circuits", IEEE transactions on CAD of IC and System [J], Vol. 21. No3. March 2002. P306-318.
7. M.Anis, S.Areibi, M.Mahmoud, and et al. Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. In the Proceeding of 39th DAC,. New Orleans, June 2002. P480-4S5.
8. Koushik K Das, Richard E Brown, " Ultra Low -Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (SOI) CMOS Technology", Proceedings of the 16th International Conference on VLSI Design (VLSI 03), 2003, New Delhi, India, P291-296.
9. Dongwoo Lee, Wesley Kwong, David Blaauw, and et al. "Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS design", in 4th International Symposium on Quality Electronic Design (ISQED), 2003, P287-292.
10. Rafik S. Guindi, Farid N. Najm, "Design Techniques for Gate-Leakage Reduction in CMOS Circuits", in 4th International Symposium on Quality Electronic Design (ISQED], 2003, P61-65.
11. D.Duarte, Y.-F Tsui, N.Vijaykrishnan, and et al. Evaluating run-time techniques for leakage power reduction. In Proceeding of 7th ASPDAC and 15th VLSI Design, Bangalore, Jan. 2002, P31-38.
12. B. J. Sheu, et al., " BS1M: Berkeley Short -Channel IGFET model for MOS Transistors", IEEE Journal of. Solid-State Circuits, vol.22 Aug. 1987. P558-566
13. S. Bobba and I. N. Hajj, "Maximum Leakage Power Estimation for CMOS Circuits", Proceedings of IEEE VOLTA99, Como, Italy, March 4-5, 1999. P116-124.
14. M, C. Johnson, D. Somasekhar and K. Roy, "Models and Algorithms for Bounds on Leakage in CMOS Circuits", IEEE Transaction on CAD of Integrated Circuits, vol,18no.6 June 1999. P714-725.
15. W.Jiang, V.Tiwari, E.Iglesia, and et al. "Topological Analysis for Leakage Prediction of Digital Circuits" In Proceeding of 7th ASPDAC and 15th VLSI Design, Bangalore, 2002. P39-44.
16. http://ww-device.eecs.berkelev.edu/ptm/introduction.ht ml
17. http://www.erc.msstate.edu/mpl/distributions/scmos/scmosdoc/index.html.