-
1
-
-
70349733881
-
Preparing for the second stage of multi-core hardware: Asymmetric cores
-
M. Gillespie, "Preparing for the second stage of multi-core hardware: Asymmetric cores," Tech. Report - Intel, 2008.
-
(2008)
Tech. Report - Intel
-
-
Gillespie, M.1
-
2
-
-
28244437702
-
Heterogeneous chip multiprocessors
-
R. Kumar, D. M. Tullsen, N. P. Jouppi, and P. Ranganathan, "Heterogeneous chip multiprocessors," Computer, 2005.
-
(2005)
Computer
-
-
Kumar, R.1
Tullsen, D.M.2
Jouppi, N.P.3
Ranganathan, P.4
-
3
-
-
56749104535
-
Efficient operating system scheduling for performance-asymmetric multi-core architectures
-
T. Li et al., "Efficient operating system scheduling for performance-asymmetric multi-core architectures," in SC, 2007.
-
(2007)
SC
-
-
Li, T.1
-
4
-
-
47249139474
-
Using asymmetric single-ISA CMPs to save energy on operating systems
-
J. C. Mogul et al., "Using asymmetric single-ISA CMPs to save energy on operating systems," IEEE Micro, 2008.
-
(2008)
IEEE Micro
-
-
Mogul, J.C.1
-
5
-
-
4644370318
-
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
-
R. Kumar et al., "Single-ISA heterogeneous multi-core architectures for multithreaded workload performance," in ISCA, 2004, p. 64.
-
(2004)
ISCA
, pp. 64
-
-
Kumar, R.1
-
6
-
-
34247174509
-
Core architecture optimization for heterogeneous chip multiprocessors
-
-, "Core architecture optimization for heterogeneous chip multiprocessors," in PACT, 2006.
-
(2006)
PACT
-
-
Kumar, R.1
-
8
-
-
70350787091
-
A dynamic scheduler for balancing hpc applications
-
C. Boneti et al., "A dynamic scheduler for balancing hpc applications," in SC '08, 2008.
-
(2008)
SC '08
-
-
Boneti, C.1
-
9
-
-
84886059374
-
Online phase detection algorithms
-
P. Nagpurkar, C. Krintz, M. Hind, P. F. Sweeney, and V. T. Rajan, "Online phase detection algorithms," in CGO, 2006.
-
(2006)
CGO
-
-
Nagpurkar, P.1
Krintz, C.2
Hind, M.3
Sweeney, P.F.4
Rajan, V.T.5
-
11
-
-
0036953769
-
Automatically characterizing large scale program behavior
-
T. Sherwood et al., "Automatically characterizing large scale program behavior," in ASPLOS-X, 2002.
-
(2002)
ASPLOS-X
-
-
Sherwood, T.1
-
13
-
-
58449134446
-
Selecting software phase markers with code structure analysis
-
J. Lau, E. Perelman, and B. Calder, "Selecting software phase markers with code structure analysis," in CGO, 2006.
-
(2006)
CGO
-
-
Lau, J.1
Perelman, E.2
Calder, B.3
-
14
-
-
0038346237
-
Positional adaptation of processors: Application to energy reduction
-
M. C. Huang et al., "Positional adaptation of processors: application to energy reduction," Comp. Arch. News, 2003.
-
(2003)
Comp. Arch. News
-
-
Huang, M.C.1
-
15
-
-
79957457267
-
-
Iowa State University, Department of Computer Science, Tech. Rep., August
-
T. Sondag and H. Rajan, "Phase-based tuning for better utilized multi-cores," Iowa State University, Department of Computer Science, Tech. Rep., August 2010.
-
(2010)
Phase-based Tuning for Better Utilized Multi-cores
-
-
Sondag, T.1
Rajan, H.2
-
17
-
-
4644271073
-
Reuse distance as a metric for cache behavior
-
K. Beyls and E. H. D'Hollander, "Reuse distance as a metric for cache behavior," in IASTED, 2001.
-
(2001)
IASTED
-
-
Beyls, K.1
D'Hollander, E.H.2
-
19
-
-
34548030923
-
Thread clustering: Sharing-aware scheduling on SMP-CMP-SMT multiprocessors
-
D. Tam, R. Azimi, and M. Stumm, "Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors," Operating Systems Review, 2007.
-
(2007)
Operating Systems Review
-
-
Tam, D.1
Azimi, R.2
Stumm, M.3
-
20
-
-
34247331460
-
Dynamic thread assignment on heterogeneous multiprocessor architectures
-
M. Becchi and P. Crowley, "Dynamic thread assignment on heterogeneous multiprocessor architectures," in CF, 2006.
-
(2006)
CF
-
-
Becchi, M.1
Crowley, P.2
-
21
-
-
0028132513
-
Atom: A system for building customized program analysis tools
-
A. Srivastava and A. Eustace, "Atom: a system for building customized program analysis tools," in PLDI '94, 1994.
-
(1994)
PLDI '94
-
-
Srivastava, A.1
Eustace, A.2
-
22
-
-
70349732456
-
Experiences and lessons learned with a portable interface to hardware performance counters
-
J. Dongarra et al., "Experiences and lessons learned with a portable interface to hardware performance counters," in PADTAD Workshop, 2003.
-
PADTAD Workshop, 2003
-
-
Dongarra, J.1
-
23
-
-
79957527146
-
Towards accurate performance evaluation using hardware counters
-
W. Mathur and J. Cook, "Towards accurate performance evaluation using hardware counters," in WSMR, 2003.
-
(2003)
WSMR
-
-
Mathur, W.1
Cook, J.2
-
24
-
-
49949106993
-
Permon2: A flexible performance monitoring interface for linux
-
S. Eranian, "permon2: a flexible performance monitoring interface for linux," in Ottawa Linux Symposium (OLS), 2006.
-
Ottawa Linux Symposium (OLS), 2006
-
-
Eranian, S.1
-
26
-
-
70349750057
-
Phase-guided thread-to-core assignment for improved utilization of performance- asymmetric multi-core processors
-
T. Sondag and H. Rajan, "Phase-guided thread-to-core assignment for improved utilization of performance- asymmetric multi-core processors," in IWMSE, May 2009.
-
IWMSE, May 2009
-
-
Sondag, T.1
Rajan, H.2
-
27
-
-
57349089252
-
Predictive thread-to-core assignment on a heterogeneous multi-core processor
-
T. Sondag, V. Krishnamurthy, and H. Rajan, "Predictive thread-to-core assignment on a heterogeneous multi-core processor," in PLOS, Oct. 2007.
-
PLOS, Oct. 2007
-
-
Sondag, T.1
Krishnamurthy, V.2
Rajan, H.3
-
28
-
-
77952283142
-
Hass: A scheduler for heterogeneous multicore systems
-
D. Shelepov et al., "Hass: a scheduler for heterogeneous multicore systems," SIGOPS Oper. Syst. Rev., vol. 43, no. 2, pp. 66-75, 2009.
-
(2009)
SIGOPS Oper. Syst. Rev.
, vol.43
, Issue.2
, pp. 66-75
-
-
Shelepov, D.1
-
29
-
-
77954592486
-
Bias scheduling in heterogeneous multi-core architectures
-
D. Koufaty, D. Reddy, and S. Hahn, "Bias scheduling in heterogeneous multi-core architectures," in EuroSys, 2010.
-
(2010)
EuroSys
-
-
Koufaty, D.1
Reddy, D.2
Hahn, S.3
-
30
-
-
67650568324
-
Scenario based optimization: A framework for statically enabling online optimizations
-
J. Mars and R. Hundt, "Scenario based optimization: A framework for statically enabling online optimizations," in CGO, 2009.
-
(2009)
CGO
-
-
Mars, J.1
Hundt, R.2
-
32
-
-
84968860873
-
Characterizing and predicting program behavior and its variability
-
E. Duesterwald et al., "Characterizing and predicting program behavior and its variability," in PACT, 2003.
-
(2003)
PACT
-
-
Duesterwald, E.1
-
33
-
-
0034461413
-
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
-
R. Balasubramonian et al., "Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures," in MICRO, 2000.
-
(2000)
MICRO
-
-
Balasubramonian, R.1
-
35
-
-
47849084514
-
Detecting change in program behavior for adaptive optimization
-
N. Peleg and B. Mendelson, "Detecting change in program behavior for adaptive optimization," in PACT, 2007.
-
(2007)
PACT
-
-
Peleg, N.1
Mendelson, B.2
-
36
-
-
34248564612
-
Exploiting program phase behavior for energy reduction on multi-configuration processors
-
F. Vandeputte, L. Eeckhout, and K. D. Bosschere, "Exploiting program phase behavior for energy reduction on multi-configuration processors," J. Sys. Archit., 2007.
-
(2007)
J. Sys. Archit.
-
-
Vandeputte, F.1
Eeckhout, L.2
Bosschere, K.D.3
-
37
-
-
34548788908
-
A practical method for quickly evaluating program optimizations
-
G. Fursin et al., "A practical method for quickly evaluating program optimizations," in HiPEAC 2005, 2005.
-
(2005)
HiPEAC 2005
-
-
Fursin, G.1
-
38
-
-
76749088304
-
Predictive runtime code scheduling for heterogeneous architectures
-
V.J. Jiménez et al., "Predictive runtime code scheduling for heterogeneous architectures," in HiPEAC '09, 2009.
-
(2009)
HiPEAC '09
-
-
Jiménez, V.J.1
-
39
-
-
17644370078
-
Best of both latency and throughput
-
E. Grochowski et al., "Best of both latency and throughput," in ICCD '04, Oct. 2004, pp. 236-243.
-
ICCD '04, Oct. 2004
, pp. 236-243
-
-
Grochowski, E.1
|