A novel concept for ultra-low capacitance via-last TSV

IEEE 3D System Integration Conference 2010, 3DIC 2010

Volumn , Issue , 2010, Pages

  Civale, Y ^a   Gonzalez, M ^a   Tezcan, D S ^a   Travaly, Y ^a   Soussan, P ^a   Beyne, E ^a  

^a IMEC   (Belgium)

Author keywords

3D interconnect; Low coupling capacitance; Through Silicon Via; via last

Indexed keywords

3D APPLICATION; 3D INTERCONNECT; COUPLING CAPACITANCE; LOW COUPLING; NOVEL CONCEPT; STRESS LEVELS; THROUGH-SILICON VIA; VIA-LAST;

INTEGRATION; THREE DIMENSIONAL;

CAPACITANCE;

EID: 79955964360     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2010.5751482     Document Type: Conference Paper

References (3)

1. E. Beyne, et al., in IEEE Technical Digest of International Electron Devices Meeting, pp. 1-4, 2008.
2. D. S. Tezcan, et al., in Proc.57th IEEE Electronic Components and Technology Conference, pp. 643-647, 2007.
3. Y. Civale, et al., in Proc. IEEE International Conference on 3D Systems Integration, 2009, pp. 1-4, 2009.