A comparison of two architectural power models

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2008, Issue , 2001, Pages 137-151

  Ghiasi, Soraya ^a   Grunwald, Dirk ^a  

^a UCB 450   (United States)

Author keywords

Architectural definition stage; Performance comparison; Power analysis tools; Validation

Indexed keywords

POWER MANAGEMENT;

ARCHITECTURE COMMUNITY; EMBEDDED DEVICE; PERFORMANCE COMPARISON; POWER ANALYSIS; PROCESSOR ARCHITECTURES; REDUCING POWER; SIMULATOR MODELS; VALIDATION;

COMPUTER ARCHITECTURE;

EID: 79955922024     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44572-2_11     Document Type: Conference Paper

References (14)

1. A. O. Allen. Probablity, Statistics, and Queueing Theory with Computer Science Applications. Academic Press.
2. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimization. In Proceedings of the 27th International Symposium on Computer Architecture, pages 83-94, Vancouver, Canada, June 2000.
3. D.C. Burger and T.M. Austin. The Simple Scalar Tool Set, Version 2.0, 1997.
4. G. Cai. Personal communication, September 2000.
5. G. Cai and C. H. Lim. Architectural level power/performance optimization and dynamic power estimation. Cool Chips Tutorial colocated with MICRO32, November 1999.
6. 2EST: A Thermal Enabled Multi-Model Power/Performance ESTimator. In Workshop on Power-Aware Computer Systems, Boston, MA, Nov 2000.
7. D. Folegnani and A. Gonzalez. Reducing Power Consumption of the Issue Logic. In Workshop on Complexity Effective Design, Vancouver, Canada, June 2000.
8. S. Ghiasi, J. Casmira, and D. Grunwald. Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption. In Workshop on Complexity Effective Design, Vancouver, Canada, June 2000.
9. R. Jain. The Art of Computer Systems Performance Analysis. Wiley Press.
10. S. Palacharla, N. P. Jouppi, and J. E. Smith. Quantifying the complexity of superscalar processors. Technical Report CS-TR-96-13-28, University of Wisconsin, November 1996.
11. S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proceedings of the 24th International Symposium on Computer Architecture, Denver, CO, June 1997.
12. J. S. Seng, D. M. Tullsen, and G. Z. N. Cai. Power sensitive multithreaded architecture. In Proceedings of the 2000 International Conference on Computer Design, 2000.
13. G. S. Sohi and S. Vajapeyam. Instruction issue logic for high-performance interruptable pipelined processors. In Proceedings of the 14th Annual Symposium on Computer Architecture, pages 27-34, 1987.
14. J. Taylor. An Introduction to Error Analysis. University Science Books.