Nanoimprint lithography for semiconductor devices and future patterning innovation

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7970, Issue , 2011, Pages

  Higashiki, Tatsuhiko ^a   Nakasugi, Tetsuro ^a   Yoneda, Ikuo ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

CD uniformity; Defect control; Lithography; Lithography investment; Nanoimprint; Overlay accuracy; Template

Indexed keywords

CD UNIFORMITY; DEFECT CONTROL; NANO-IMPRINT; OVERLAY ACCURACY; TEMPLATE;

DEFECTS; INNOVATION; PRODUCTION; SEMICONDUCTOR SWITCHES; SHRINKAGE; TECHNOLOGY;

NANOIMPRINT LITHOGRAPHY;

EID: 79955902986     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.882940     Document Type: Conference Paper

References (6)

1. M. Smith, "Step and Flash Imprint Lithography for Silicon Circuit Applications", proc of SPIE2007
2. I. Yoneda, et al, "Nanoimprint applications toward 22nm node CMOS devices", proc. of MNE, Sep. 2007
3. T. Higashiki, "Status and Future Lithography for Sub-hp32nm Device", Lithography Workshop 2007, Dec. 2007
4. N. Hayashi, "Nanoimprint Lithography Template Technology; Progress and issue", Lithography Workshop 2010 (Nov.)
5. T. Nakasugi et al, "A Consideration of Desktop Lithography", Litho Extension 2010, Oct.2010
6. P. Maury, et al, "Roll-to-roll UV imprint lithography for flexible electronics", P-LITH-98, MNE2010, Sept.2010