3D Packaging Technology: Enabling the next wave of applications

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2010, Pages

  Bolanos, Mario A ^a  

^a TEXAS INSTRUMENTS   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

3D PACKAGING; ELECTRONIC PRODUCT; EXPECTED VALUES; HETEROGENEOUS TECHNOLOGY; MEGATRENDS; PACKAGING TECHNOLOGIES; POWER MANAGEMENTS; SEMICONDUCTOR INDUSTRY; SMART ELECTRONICS; STORAGE DEVICES; SYSTEM IN PACKAGE; THROUGH SILICON VIAS; VALUE ADDED APPLICATIONS; VOLUME PRODUCTION;

ENERGY HARVESTING; ENERGY MANAGEMENT; INDUSTRIAL ELECTRONICS; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; SIGNAL PROCESSING; TECHNOLOGY; THREE DIMENSIONAL; VIRTUAL STORAGE;

PACKAGING;

EID: 79955760667     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEMT.2010.5746735     Document Type: Conference Paper

References (5)

1. Prior, Brandon, Prismark LLC. IMAPS Device Packaging Conference, Phoenix, Arizona, 2010
2. Prior, Brandon, Prismark LLC. IMAPS Device Packaging Conference, Phoenix, Arizona, 2010
3. Bolanos, Mario, Texas Instruments. Con Fab Conference, Las Vegas, Nevada, 2010
4. Bolanos, Mario, Texas Instruments. "Power Integrity Analysis and Management for Integrated Circuits" by Raj Nair and Donald Bennett (ISBN 0137011229), Pearson Education (Prentice Hall Professional), Ch. 10.
5. Bolanos, Mario, Texas Instruments. SEMICON Singapore, Singapore, 2008. "Main Drivers of Semiconductor Integrated Circuit Packaging Technology Research and Development in the Next Decade".