A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 188-189

  Wei, Hegong ^a   Chan, Chi Hang ^a   Chio, U Fat ^a   Sin, Sai Weng ^a   Seng Pan, U ^a   Martins, Rui ^a,b   Maloberti, Franco ^c  

^a UNIVERSITY OF MACAU   (Macao)

^b INSTITUTO SUPERIOR TÉCNICO   (Portugal)

^c UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION ALGORITHMS; APPROXIMATION THEORY; BANDWIDTH; CLOCKS; INTEGRATED CIRCUIT DESIGN; SHIFT REGISTERS;

BIT RESOLUTION; CONVERSION RATES; CROSS-COUPLED; DESIGN SOLUTIONS; LOW-BANDWIDTH; NANOMETER CMOS; SUCCESSIVE APPROXIMATION METHODS; SUCCESSIVE APPROXIMATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 79955746515     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746276     Document Type: Conference Paper

References (5)

1. W. Liu, Y. Chang, S.-K. Hsien, et al., "A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization," ISSCC Dig. Tech. Papers, pp. 82-83, Feb., 2009.
2. Z. Cao, S. Yan, and Y. Li, "A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 542-543, Feb., 2008.
3. Y. Shimizu, S. Murayama, K. Kudoh, and H. Yatsuda, "A Split-Load Interpolation-Amplifier-Array 300MS/s 8b Subranging ADC in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 552-553, Feb., 2008.
4. L. Brooks and H.-S. Lee, "A Zero-Crossing-Based 8b 200MSs Pipelined ADC," ISSCC Dig. Tech. Papers, pp. 460-461, Feb., 2007.
5. Y.-D. Jeon, Y.-K. Cho, J.-W. Nam, et al., "A 9.15mW 0.22mm2 10b 204MS/s Pipelined SAR ADC in 65nm CMOS," IEEE CICC, Sept., 2010.