A low-power process-scalable superheterodyne receiver with integrated high-Q filters

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 60-61

  Mirzaei, Ahmad ^a   Darabi, Hooman ^a   Murphy, David ^b  

^a BROADCOM CORPORATION   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HETERODYNING;

CHANNEL SELECTION; IMAGE REJECTION; INTEGRATED RECEIVERS; LEVEL OF INTEGRATIONS; SCALABILITY ISSUE; SIMPLE STRUCTURES; SUPER-HETERODYNE ARCHITECTURE; SUPERHETERODYNE RECEIVERS;

LOW PASS FILTERS;

EID: 79955710073     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746219     Document Type: Conference Paper

References (3)

1. A. Mirzaei, et. al., "A 65nm CMOS Quad-Band SAW-less Receiver for GSM/GPRS/EDGE", IEEE VLSI Symposium, pp. 179-180, 2010.
2. A. Ghaffari, et. al., "A Differential 4-Path Highly Linear Widely Tunable On-Chip Bandpass Filter", IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 299-302, 2010.
3. D. V. Grunigen, and et. al., "An Integrated CMOS Switched-Capacitor Bandpass Filter Based on N-path and Frequency-Sampling Principles," IEEE Journal of Solid-State Circuits, vol. SC-18, no. 6, pp. 753-761, 1983.