On the fault tolerance of a clustered single-electron neural network for differential enhancement

IEICE Electronics Express

Volumn 2, Issue 3, 2005, Pages 76-80

  Oya, Takahide ^a   Schmid, Alexandre ^b   Asai, Tetsuya ^a   Leblebici, Yusuf ^b   Amemiya, Yoshihito ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

^b EPFL   (Switzerland)

Author keywords

fault tolerance; neural network; single electron circuit

Indexed keywords

EID: 79955536412     PISSN: 13492543     EISSN: None     Source Type: Journal    
DOI: 10.1587/elex.2.76     Document Type: Article

References (5)

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2. A. Schmid and Y. Leblebici, “Robust Circuit and System Design Methodologies for Nanometer-Scale Devices and Single-Electron Transistors,” Proc. IEEE-NANO03, vol. 2, pp. 516-519, 2003.
3. T. Oya, T. Asai, R. Kagaya, T. Hirose, and Y. Amemiya, “Neuromorphic Single-Electron Circuit and Its Application to Temporal-Domain Neural Competition,” Proc. 2004 Int. Symp. on NOLTA, pp. 235-239, 2004.
4. T. Oya, T. Asai, T. Fukui, and Y. Amemiya, “Reaction-Diffusion Systems Consisting of Single-Electron Oscillators,” Int. J. Unconventional Computing, vol. 1, no. 2, 2005.
5. T. Yamada, M. Akazawa, T. Asai, and Y. Amemiya, “Boltzmann machine neural network devices using single-electron tunneling,” Nanotechnology, vol. 12, no. 1, pp. 60-67, 2001.