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Volumn 60, Issue 1, 2011, Pages 53-57

Ge1-xSnx stressors for strained-Ge CMOS

(14) Takeuchi, S a,h Shimura, Y a,b Nishimura, T a Vincent, B c Eneman, G c,d,e Clarysse, T c Demeulemeester, J f Vantomme, A f Dekoster, J c Caymax, M c Loo, R c Sakai, A g Nakatsuka, O a Zaima, S a

a NAGOYA UNIVERSITY (Japan)

b JAPAN SOCIETY FOR THE PROMOTION OF SCIENCE (Japan)

c IMEC (Belgium)

d UNIVERSITY OF LEUVEN (Belgium)

e RESEARCH FOUNDATION FLANDERS FWO (Belgium)

f KU LEUVEN (Belgium)

g OSAKA UNIVERSITY (Japan)

h Covalent Silicon Corporation (Japan)

Author keywords

GeSn materials; GeSn thermal budget; Source drain engineering; Strained Ge pMOSFET

Indexed keywords

ANNEALING TEMPERATURES; B IMPLANTATION; CHANNEL REGION; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; CRYSTAL DAMAGE; CRYSTALLINE QUALITY; DEFECT GENERATION; DISLOCATION GENERATION; GA DOPING; GA-DOPED; GESN MATERIALS; IN-SITU; LOW THERMAL BUDGET; P-TYPE; POLYCRYSTALLINE; SOLID PHASE EPITAXIAL REGROWTH; SOURCE/DRAIN ENGINEERING; STRAINED-GE; STRAINED-SI; THERMAL BUDGET;

AGGLOMERATION; BUDGET CONTROL; DEFECTS; DISLOCATIONS (CRYSTALS); EPITAXIAL GROWTH; GERMANIUM; MOSFET DEVICES; POINT DEFECTS; SEMICONDUCTOR DOPING; SURFACE ROUGHNESS;

TIN;

EID: 79955523675 PISSN: 00381101 EISSN: None Source Type: Journal
DOI: 10.1016/j.sse.2011.01.022 Document Type: Article

Times cited : (39)

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