IBM power edge of network processor: A wire-speed system on a chip

IEEE Micro

Volumn 31, Issue 2, 2011, Pages 76-85

  Brown, Jeffrey ^a   Woodward, Sandra ^a   Bass, Brian ^a   Johnson, Charlie ^a  

^a IBM   (United States)

Author keywords

data encryption; microarchitecture implementation considerations; Multicore multiprocessors; network level security and protection; on chip interconnection networks; parallel architectures; processor architectures; single chip multiprocessors; support for multithreaded execution

Indexed keywords

DATA ENCRYPTION; MICROARCHITECTURE IMPLEMENTATION CONSIDERATIONS; MULTI CORE; NETWORK-LEVEL SECURITY AND PROTECTION; ON-CHIP INTERCONNECTION NETWORK; PROCESSOR ARCHITECTURES; SINGLE-CHIP MULTIPROCESSORS;

CRYPTOGRAPHY; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NANOTECHNOLOGY; NETWORK SECURITY; PARALLEL ARCHITECTURES; TELECOMMUNICATION NETWORKS;

NETWORK ARCHITECTURE;

EID: 79955430619     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2011.3     Document Type: Conference Paper

References (5)

1. D.P. LaPotin et al., "Workload and Network-Optimized Computing Systems," IBM J. Research and Development, vol. 54, no. 1, 2010, pp. 1:1-1:12.
2. H.O. Le et al., "IBM Power6 Microarchitecture," IBM J. Research and Development, vol. 51, no. 6, 2007, pp. 669-662.
3. D.M. Tullsen, S.J. Eggers, and H.M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," Proc. 22nd Ann. Int'l Symp. Computer Architecture, IEEE Press, 1995, pp. 392-403.
4. J. van Lunteren, "High-Performance Pattern-Matching for Intrusion Detection," Proc. 25th IEEE Int'l Conf. Computer Comm., IEEE Press, 2006, doi:10.1109/ INFOCOM.2006.204.
5. R. Salz, H. Achilles, and D. Maze, "Hardware and Software Trade-offs in the IBM DataPower XML XG4 Processor Card," Proc. Int'l Symp. Processing XML Efficiently: Overcoming Limits on Space, Time, or Bandwidth, Balisage, 2009, vol. 4, doi:10.4242/BalisageVol4.Salz01.