Pipelined floating point arithmetic optimized for FPGA architectures

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1673, Issue , 1999, Pages 365-370

  Stamoulis, Iakovos ^a   White, Martin ^a   Lister, Paul F ^a  

^a UNIVERSITY OF SUSSEX   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUIT DESIGN; NUMBER THEORY; PIPELINES; THREE DIMENSIONAL COMPUTER GRAPHICS;

3D COMPUTER GRAPHICS; ALTERNATIVE ALGORITHMS; ARITHMETIC UNIT; EFFICIENT ARCHITECTURE; FLOATING POINT UNITS; FPGA ARCHITECTURES; LOGIC FUNCTIONS; SYNTHESIS TOOL;

COMPUTER ARCHITECTURE;

EID: 79955160166     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-48302-1_39     Document Type: Conference Paper

References (9)

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2. John L. Hennesy & David A. Patterson “Computer Architecture, A Quantitative Approach” Morgan Kaufmann Publishers, Inc. ISBN 1-55860-188-0
3. Stuart F. Oberman and Michael J. Flynn, “Design Issues in Division and other Floating-Point Operations”, IEEE Transactions on Computers, Vol.46 No.2 February 1997.
4. Nabeel Shirazi, Al Walters and Peter Athanas, “Quantitative Analysis of Floating Point arithmetic on FPGA based Custom Computing Machines.” Virginia Polytechnic Institute and State University, Proceeding of IEEE Symposium on FPGAs for Custom Computing Machines, April 1995
5. Joseph J. F. Cavanagh, “Digital Computer Arithemetic - Design and implementation”, McGraw-Hill Book Company, 1985, ISBN 0-07-Y66213-4
6. Iakovos Stamoulis, Nicky Ford, Martin White, Graham J. Dunnett, Paul F. Lister, “VHDL Methodologies for effective implementation in FPGA devices and subsequent transition to ASIC technology”, Designer Track DATE ‘98, Paris 23-26 February 1998.
7. Lucent Technologies, “ORCA OR2C Field Programmable Gate Arrays”, Users’ Manual, January 1998.
8. Synplicity, Inc. “Synplify, Simply Better Synthesis”, User’s Guide Version 3.0 with HDL Analyst”, July 1997.
9. Synopsys, Inc. “FPGA Express” Version 2.0.1, Users’ Manual, P/N 01733-000 DB February 1998