FPGA-based modelling unit for high speed lossless arithmetic coding

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2147, Issue , 2001, Pages 643-647

  Stefo, Riad ^a   Núñez, José Luis ^b   Feregrino, Claudia ^b   Mahapatra, Sudipta ^c   Jones, Simon ^b  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

^b LOUGHBOROUGH UNIVERSITY   (United Kingdom)

^c NATIONAL INSTITUTE OF TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER CIRCUITS; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

ADAPTIVE MODELLING; ARITHMETIC CODING; BASED MODELLING; BINARY ARITHMETIC CODING; CLOCK CYCLES; CODING PROCESS; HARDWARE IMPLEMENTATIONS; SIMPLE METHOD;

CODES (SYMBOLS);

EID: 79955140470     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44687-7_71     Document Type: Conference Paper

References (8)

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