Multithreading for logic-centric systems

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 5-14

  Brebner, Gordon ^a,b  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

^b XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; LOGIC CIRCUITS; MULTITASKING; RECONFIGURABLE ARCHITECTURES; SYSTEM-ON-CHIP;

LEVEL MODEL; LOGIC CIRCUITRY; LOGIC-CENTRIC SYSTEMS; MULTI-THREADING; MULTI-VERSION; PROGRAMMABLE LOGIC; SYSTEMS ON CHIPS; TIME SLICING;

COMPUTER CIRCUITS;

EID: 79955139590     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_3     Document Type: Conference Paper

References (13)

1. F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, C. Passerone, A. Sangiovanni-Vincentelli, E. Sentovich, K. Suzuki and B. Tabbara. Hardware-Software Co-Design of Embedded Systems: The Polis Approach. Kluwer Academic Press, 1997.
2. N. Bergmann, G. Brebner and J. Gray. Reconfigurable computing and reactive systems. Proc. 7th Australasian Conference on Parallel and Real-Time Systems, Springer, 2000, pages 171-180.
3. F. Braun, J. Lockwood and M. Waldvogel. Reconfigurable router modules using network protocol wrappers. Proc. 11th International Conference on Field Programmable Logic and Applications, Springer LNCS 2147, 2001, pages 254-263. (Pubitemid 33335348)
4. G. Brebner. A virtual hardware operating system for the Xilinx XC6200. Proc. 6th International Workshop on Field Programmable Logic and Applications, Springer LNCS 1142, 1996, pages 327-336. (Pubitemid 126136691)
5. G. Brebner and O. Diessel. Chip-based reconfigurable task management. Proc. 11th International Conference on Field Programmable Logic and Applications, Springer LNCS 2147, 2001, pages 182-191. (Pubitemid 33335340)
6. G. Brebner. Single-chip gigabit mixed-version IP router on Virtex-II Pro. Proc. 10th Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 2002, to appear.
7. J. Burns, A. Donlin, J. Hogg, S. Singh and M. de Wit. A dynamic reconfiguration run-time system. Proc. 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, 1997, pages 66-75.
8. O. Diessel and H. ElGindy. Run-time compaction of FPGA designs. Proc. 7th International Workshop on Field Programmable Logic and Applications, Springer LNCS 1304, 1997, pages 131-140. (Pubitemid 127118747)
9. H. ElGindy, M. Middendorf, H. Schmeck and B. Schmidt. Task rearrangement on partially reconfigurable FPGAs with restricted buffer. Proc. 10th International Workshop on Field Programmable Logic and Applications, Springer LNCS 1896, 2000, pages 379-388.
10. H. Fallside and M. Smith. Internet Connected FPL. Proc. 10th International Workshop on Field Programmable Logic and Applications, Springer LNCS 1896, 2000, pages 48-57.
11. D. Harel. Statecharts: a visual formalism for complex systems. Science of Computer Programming, 8, June 1987, pages 231-274. (Pubitemid 17617706)
12. A. Silberschatz, P. Galvin and G. Gagne. Applied Operating System Concepts (1st edition). New York: Wiley, 2000.
13. Xilinx Inc. Platform FPGAs. http://www.xilinx.com/products/platform/