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Volumn , Issue , 2011, Pages

Hardware-in-the-Loop (HIL) to reduce the development cost of power electronic converters

Author keywords

Control; FPGA; HIL; Multi level converter; Power quality; Real time simulation

Indexed keywords

DESIGN PROCESS; DEVELOPMENT COSTS; EFFECTIVE TOOL; FPGA; FPGA BOARDS; HARDWARE-IN-THE-LOOP; HIL; LONG TERM; MULTI-LEVEL CONVERTER; OFFLINE; POWER ELECTRONIC CONVERTERS; REAL-TIME SIMULATION; REAL-TIME SIMULATOR; SIMULATION RESULT; VALIDATION METHODOLOGIES; VIRTUAL TESTING; HARDWARE IN THE LOOPS; MULTILEVEL CONVERTER; REAL TIME SIMULATIONS; REAL TIME SIMULATORS;

EID: 79953137243     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IICPE.2011.5728153     Document Type: Conference Paper
Times cited : (21)

References (7)
  • 5
    • 72449164983 scopus 로고    scopus 로고
    • A novel high efficient fifteen level power converter
    • 20-24 September San Jose, California, USA
    • Y. Ounejjar and K. Al-Haddad "A novel high efficient fifteen level power converter", IEEE Energy Conversion Congress and Exposition ECCE, pp. 2139-2144, 20-24 September 2009, San Jose, California, USA
    • (2009) IEEE Energy Conversion Congress and Exposition ECCE , pp. 2139-2144
    • Ounejjar, Y.1    Al-Haddad, K.2
  • 6
    • 77950121565 scopus 로고    scopus 로고
    • A new high power efficiency cascaded U cells multilevel converter
    • 5-8 July Seoul, Korea
    • Y. Ounejjar and K. Al-Haddad "A new high power efficiency cascaded U cells multilevel converter", IEEE ISIE, pp. 483 - 488, 5-8 July 2009, Seoul, Korea
    • (2009) IEEE ISIE , pp. 483-488
    • Ounejjar, Y.1    Al-Haddad, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.