Predictable worst-case execution time analysis for multiprocessor systems-on-chip

Proceedings - 2011 6th IEEE International Symposium on Electronic Design, Test and Application, DELTA 2011

Volumn , Issue , 2011, Pages 99-104

  Rosén, Jakob ^a   Eles, Petru ^a   Peng, Zebo ^a   Andrei, Alexandru ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b ERICSSON RESEARCH   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL POWER; EMBEDDED APPLICATION; HARDWARE PLATFORM; MULTI PROCESSOR ARCHITECTURE; MULTI PROCESSOR SYSTEMS; MULTIPROCESSOR SYSTEMS ON CHIPS; REAL-TIME SYSTEM DESIGNS; WORST-CASE ANALYSIS; WORST-CASE EXECUTION TIME ANALYSIS;

DESIGN; FAULT TOLERANCE; MULTIPROCESSING SYSTEMS; REAL TIME SYSTEMS; SYSTEMS ANALYSIS;

QUALITY ASSURANCE;

EID: 79953127632     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DELTA.2011.27     Document Type: Conference Paper

References (14)

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