An efficient dual-mode floating-point multiply-add fused unit

2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings

Volumn , Issue , 2010, Pages 5-8

  Manolopoulos, K ^a   Reisis, D ^a   Chouliaras, V A ^b  

^a UNIVERSITY OF ATHENS   (Greece)

^b LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL MODES; DUAL PATH; FLOATING-POINT ADDITION; LOW LATENCY; MULTIPLY-ADD FUSED;

DIGITAL ARITHMETIC;

EID: 79953116880     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2010.5724440     Document Type: Conference Paper

References (13)

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