A 2.1 μW area-efficient capacitively-coupled chopper instrumentation amplifier for ECG applications in 65 nm CMOS

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Volumn , Issue , 2010, Pages 337-340

  Fan, Qinwen ^a   Sebastiano, Fabio ^b   Huijsing, Han ^a   Makinwa, Kofi ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; AREA EFFICIENT; CAPACITIVE FEEDBACK; CORNER FREQUENCY; DC OFFSETS; DC SERVO; ELECTRODE-TISSUE INTERFACE; FEED-BACK LOOP; HIGH-PASS; INSTRUMENTATION AMPLIFIER; SERVO LOOPS; SWITCHED CAPACITOR INTEGRATOR;

CMOS INTEGRATED CIRCUITS; ELECTROCHROMIC DEVICES; INSTRUMENTS;

ELECTROCARDIOGRAPHY;

EID: 79952858291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2010.5716624     Document Type: Conference Paper

References (7)

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7. Q.Fan, H. Huisjing and K. Makinwa, "A 1.8μW 1μV-Offset Capacitively-Coupled Chopper Instrumentation Amplifier in 65nm CMOS," IEEE, ESSCIRC, Sep. 2010. (accepted)