A 3-GS/s 5-bit 36-mW flash ADC in 65-nm CMOS

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Volumn , Issue , 2010, Pages 181-184

  Ito, Tomohiko ^a   Itakura, Tetsuro ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; CALIBRATION METHOD; CLOCK BUFFER; DC OFFSETS; FLASH-ADC; INPUT FREQUENCY; MILLIMETER-WAVE COMMUNICATION; NYQUIST; RESISTOR LADDER;

CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS;

DC POWER TRANSMISSION;

EID: 79952850013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2010.5716585     Document Type: Conference Paper

References (11)

1. Y. Nakajima, A. Sakaguchi, T. Ohkido, N. Kato, T. Matsumoto, and M. Yotsuyanagi, "A Background Self-Calibrated 6b 2.7GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture," IEEE J. of Solid-State Circuits, pp. 707-718, Apr. 2010.
2. M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D Converter in 0.35-μm CMOS," IEEE J. of Solid-State Circuits, vol. 36, pp. 1847-1858, Dec. 2001.
3. Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, and H. Ikawa, "A 400MSPS 8b Flash AD Conversion LSI," in Proc. of IEEE International Solid-State Circuits Conf., pp. 98-99, Feb. 1987.
4. K. Uyttenhove and M. S. J. Steyaert, "A 1.8-V 6-Bit 1.3 GHz Flash ADC in 0.25-μm CMOS," IEEE J. of Solid-State Circuits, pp. 1115-1122, Jul. 2003.
5. S. Park, Y. Palaskas, and M. P. Flynn, "A 4-GS/s 4-bit Flash ADC in 0.18-μm CMOS," IEEE J. of Solid-State Circuits, pp. 1865-1872, Sep. 2007.
6. K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, and T. Miki, "A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS," IEEE J. of Solid-State Circuits, vol. 43, pp. 2303-2310, Oct. 2008.
7. E. Alpman, H. Lakdawala, L. R. Carley, and K. Soumyanath, "A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS," in Proc. of IEEE International Solid-State Circuits Conf., pp. 76-77, Feb. 2009.
8. B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. V. der Plas, "A 2.6mW 6b 2.2GS/s 4-times Interleaved Fully Dynamic Pipelined ADC in 40nm Digital CMOS," in Proc. of IEEE International Solid-State Circuits Conf., pp. 296-297, Feb. 2010.
9. S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, "A 3.5-GS/s 5-b Flash ADC in 90 nm CMOS," in Proc. IEEE Custom Integrated Circuits Conf., pp. 489-492, Sep. 2006.
10. Y.-Z. Lin, Y.-T. Liu, and S.-J. Chang, "A 5-bit 4.2-GS/s Flash ADC in 0.13-μm CMOS," in Proc. IEEE Custom Integrated Circuits Conf., pp. 213-216, Sep. 2007.
11. M. Kijima, K. Ito, K. Kamei, and S. Tsukamoto, "A 6b 3GS/s Flash ADC with Background Calibration," in Proc. IEEE Custom Integrated Circuits Conf., pp. 283-286, Sep. 2009.