An approach to tolerate process related variations in memristor-based applications

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2011, Pages 18-23

  Rajendran, Jeyavijayan ^a   Maenm, Harika ^a   Karri, Ramesh ^a   Rose, Garrett S ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL LOGIC; ELECTRONIC DEVICE; MEMRISTOR; NON-LINEAR RELATIONSHIPS; OXIDE LAYER; PROCESS VARIATION; PROCESS-INDUCED VARIATION; THRESHOLD GATES;

BOOLEAN FUNCTIONS; DESIGN; MEMRISTORS; NEURAL NETWORKS; PASSIVE FILTERS; RESISTORS; THRESHOLD LOGIC;

EMBEDDED SYSTEMS;

EID: 79952824977     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2011.49     Document Type: Conference Paper

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