Unified parallel C for GPU clusters: Language extensions and compiler implementation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 6548 LNCS, Issue , 2011, Pages 151-165

  Chen, Li ^a   Liu, Lei ^a   Tang, Shenglin ^a   Huang, Lei ^b   Jing, Zheng ^a   Xu, Shixiong ^a   Zhang, Dingfei ^a   Shou, Baojiang ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

^b University of Houston ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODE GENERATION; COMPILE TIME; COMPILER IMPLEMENTATION; DATA MANAGEMENT; EXECUTION MODEL; GPU CLUSTERS; GRAPHICS PROCESSING UNITS; HIERARCHICAL DATA; HIGH PERFORMANCE COMPUTING; LANGUAGE EXTENSIONS; LOOP TILING; MEMORY LAYOUT; MEMORY MODULES; MEMORY OPTIMIZATION; PARALLEL MACHINE; PROGRAMMABILITY; RUNTIME OPTIMIZATION; UNIFIED PARALLEL C;

CACHE MEMORY; COMPUTER SOFTWARE SELECTION AND EVALUATION; DATA TRANSFER; INFORMATION MANAGEMENT; OPTIMIZATION; PARALLEL ARCHITECTURES; SEMANTICS;

PROGRAM COMPILERS;

EID: 79952596877     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-19595-2_11     Document Type: Conference Paper

References (17)

1. Fatahalian, K., Knight, T., Houston, M., Erez, M., Horn, D., Leem, L., Park, H., Ren, M., Aiken, A., Dally, W., Hanrahan, P.: Sequoia: Programming the Memory Hierarchy. In: Proceedings of Supercomputing 2006 (November 2006)
2. Yan, Y., Zhao, J., Guo, Y., Sarkar, V.: Hierarchical place trees: A portable abstraction for task parallelism and data movement. In: Gao, G.R., Pollock, L.L., Cavazos, J., Li, X. (eds.) LCPC 2009. LNCS, vol. 5898, pp. 172-187. Springer, Heidelberg (2010)
3. Bikshandi, G., Guo, J., Hoeflinger, D., Almasi, G., Fraguela, B.B., Garzarán, M.J., Padua, D., von Praun, C.: Programming for parallelism and locality with hierarchically tiled arrays. In: PPoPP, New York, USA, March 29-31 (2006)
4. Nishtala, R., Almasi, G., Cascaval, C.: Performance without pain = productivity: data layout and collective communication in UPC. In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2008 (2008)
5. Ueng, S., Lathara, M., Baghsorkhi, S.S., Hwu, W.W.: CUDA-lite: Reducing GPU programming complexity. In: Amaral, J.N. (ed.) LCPC 2008. LNCS, vol. 5335, pp. 1-15. Springer, Heidelberg (2008)
6. Han, T.D., Abdelrahman, T.S.: hiCUDA: a high-level directive-based language for GPU programming. In: Workshop on General Purpose Processing on Graphics Processing Units (GPGPU), pp. 52-61 (March 2009)
7. Yan, Y., et al.: JCUDA: a Programmer-Friendly Interface for Accelerating Java Programs with CUDA. In: Sips, H., Epema, D., Lin, H.-X. (eds.) Euro-Par 2009. LNCS, vol. 5704, pp. 887-899. Springer, Heidelberg (2009)
8. Lee, S., Min, S.-J., Eigenmann, R.: OpenMP to GPGPU: a compiler framework for automatic translation and optimization. In: ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), pp. 101-110 (February 2009)
9. The Portland Group. PGI Fortran &C Accelerator Programming Model (March 2010), http://grape.pgroup.com/lit/whitepapers/ pgi-accel-prog-model-1.2. pdf
10. http://www.caps-entreprise.com/fr/ page/index.php?id=49&p-p=36
11. NVIDIA CUDA, China campus programming contest (2009), http://cuda.csdn.net/contest/pro
12. Yang, Y., Xiang, P., Kong, J., Zhou, H.: A GPGPU Compiler for Memory Optimization and Parallelism Management. In: The ACM SIGNPLAN 2010 Conference on Programming Language Design and Implementation, PLDI 2010 (June 2010)
13. Serres, O., Kayi, A., Anbar, A., El-Ghazawi, T.: A UPC Specification Extension Proposal for Hierarchical Parallelism. In: The 3rd Conference on Partitioned Global Address Space Programming Models, Virginia, USA (October 2009)
14. Numrich, R.: Teams for Co-Array Fortran. In: The 3rd Conference on Partitioned Global Address Space Programming Models, Virginia, USA (October 2009)
15. Barton, C., Casçaval, C., Almási, G., Zheng, Y., Farreras, M., Chatterje, S., Amaral, J.N.: Shared memory programming for large scale machines. In: Proceedings of the 2006 ACM SIGPLAN Conference on Programming Language Design and Implementation, Ottawa, Ontario, Canada, June 11-14 (2006)
16. Husbands, P., Iancu, C., Yelick, K.: A performance analysis of the Berkeley UPC compiler. In: Proceedings of the 17th Annual International Conference on Supercomputing, San Francisco, CA, USA, June 23-26 (2003)
17. Bauer, M., Clark, J., Schkufza, E., Aiken, A.: Sequoia++ User Manual, http://sequoia.stanford.edu/