A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness

Proceedings of CASCON - 1st Decade High Impact Papers

Volumn , Issue , 2010, Pages 146-158

  Bacon, David F ^a   Chow, Jyh Herng ^a   Ju, Dz Ching R ^a   Muthukumar, Kalyan ^a   Sarkar, Vivek ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAY DIMENSIONS; ARRAY VARIABLES; CACHE MISS; DATA DECLARATION; LOOP ITERATION; MEMORY ACCESS; POLYNOMIAL TIME COMPLEXITY; STATIC AND DYNAMIC; TRANSLATION LOOKASIDE BUFFER;

HEURISTIC ALGORITHMS; POLYNOMIAL APPROXIMATION;

BUFFER STORAGE;

EID: 79952145180     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1925805.1925813     Document Type: Conference Paper

References (12)

1. PF77 Shared Memory Parallelizer and Precompiler for the IBM POWER/4 System User's Guide (Preliminary Draft), 1993. Applied Parallel Research.
2. David Bailey. Unfavorable Strides in Cache Memory Systems. Technical Report RNR-92-015, NASA Ames Research Center, CA, 1992.
3. Jeanne Ferrante, Vivek Sarkar, and Wendy Thrash. On Estimating and Enhancing Cache Effectiveness. Lecture Notes in Computer Science, (589), 1991. Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing, Santa Clara, California, USA, August 1991. Edited by U. Banerjee, D. Gelernter, A. Nicolau, D. Padua.
4. Elana D. Granston. Toward a Compile-Time Methodology for Reducing False Sharing and Communication Traffic in Shared Virtual Memory Systems. In Proc. of Sixth Workshop on Language and Compilers for Parallel Computing, 1993.
5. Manish Gupta and David A. Padua. Effects of Program Parallelization and Stripmining Transformation on Cache Performance in a Multiprocessor. In International Conference on Parallel Processing, pages 1.301-1.304, 1991.
6. High Performance Fortran Forum. High Performance Fortran. Language Specification-Version 0.4, December 1992.
7. Monica S. Lam, Edward E. Rothberg, and Michael E. Wolf. The Cache Performance and Optimizations of Blocked Algorithms. In ACM International Conference on Architectural Support for Programming Languages and Operating Systems, pages 63-74, 1991.
8. D.H. Lawrie and C. R. Vora. The prime memory system for array access. IEEE Trans. on Computers, C-31(5):435-442, October 1982.
9. Olivier Temam, Elana Granston, and William Jalby. To Copy or Not to Copy: A Compile-Time Technique for Assessing When Data Copying Should be Used to Eliminate Cache Conflicts. In Proc. Supercomputing '93, pages 410-419, 1993.
10. Josep Torrellas, Monica S. Lam, and John L. Hennessy. Shared Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates. In International Conference on Parallel Processing, pages II.266-II.270, 1990.
11. Steven W. White. POWER2: Architecture and Performance. In Proceedings of COMP-CON '94, pages 384-388, 1994.
12. Michael E. Wolf and Monica S. Lam. A Data Locality Optimizing Algorithm. In ACM Sigplan Conference on Programming Language Design and Implementation, pages 30-44, 1991.