Edge current induced failure of semiconductor PN junction during operation in the breakdown region of electrical characteristic

Microelectronics Reliability

Volumn 51, Issue 3, 2011, Pages 536-542

  Obreja, V V N ^a   Codreanu, C ^a   Poenar, D ^b   Buiu, O ^c  

^a NATIONAL INSTITUTE FOR RESEARCH AND DEVELOPMENT IN MICROTECHNOLOGIES   (Romania)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c UNIVERSITY OF LIVERPOOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

A-SPOTS; APPLIED VOLTAGES; ATOMIC LAYER; AVALANCHE BREAKDOWN; AVALANCHE MULTIPLICATION; CURRENT FLOWS; CURRENT INCREASE; DEVICE DATA; DEVICE FAILURES; EDGE CURRENTS; ELECTRICAL CHARACTERISTIC; FIXED CHARGES; HIGH VOLTAGE; INTERFACIAL LAYER; IV CHARACTERISTICS; JUNCTION TEMPERATURES; LINEAR VARIATION; MATERIAL DEGRADATION; MATERIAL INTERFACES; P-N JUNCTION; PASSIVATION PROCESS; POWER MOSFETS; REVERSE CURRENTS; REVERSE VOLTAGES; SHORT DURATIONS; SILICON DEVICES; SINGLE PULSE; SOFT BREAKDOWN; VOLTAGE DEPENDENCE;

AVALANCHE DIODES; DEGRADATION; DIELECTRIC MATERIALS; DIODES; MOSFET DEVICES; PASSIVATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DIODES;

SEMICONDUCTOR JUNCTIONS;

EID: 79951944998     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.10.011     Document Type: Article

References (30)

1. O.M. Clark Transient voltage suppressor types and application IEEE Trans Power Electron 5 1990 20 26
2. H. Egawa Avalanche characteristics and failure mechanism of high voltage diodes IEEE Trans Electron Dev 13 1966 754 758
3. B. Bazin Silicon avalanche diode behavior for 10 μs surge current in reverse direction Solid State Electron 10 1967 509 511
4. P.A. Tove Methods of avoiding edge effects on semiconductor diodes J Phys D: Appl Phys 15 1982 517 536 (Pubitemid 12539681)
5. S. Salkalachen, N. Krishnan, S. Krishnan, H. Satyamurthy, and K. Srinivas Edge passivation and related electrical stability in silicon power devices IEEE Trans Semicond Manuf 3 1990 12 17 (Pubitemid 20666020)
6. Trost JR, Ridley RS, Kamal Khan M, Grebs T. The effect of charge in junction termination extension passivation dielectrics. In: Proc 11th int symp power semiconductor devices and ICs; 1999. p.189-92.
7. 4 passivation of high power rectifiers IEEE Trans Electron Dev 17 1970 797 800
8. A. Czerwinski, E. Simoen, A. Poyai, and C. Claeys Peripheral current analysis of silicon p-n junction and gated diodes J Appl Phys 88 11 2000 6506 6514
9. W. Wondrak Physical limits and lifetime limitations of semiconductor devices at high temperature Microelectron Reliab 39 1999 1113 1120 (Pubitemid 129304842)
10. Obreja VVN, Codreanu C, Poenar D, Buiu O. Semiconductor PN juncion failure at operation near or in the breakdown region of the reverse I-V characteristic. In: Proceedings IEEE 12th international symposium on the physical & failure analysis of integrated circuits (IPFA2005); 2005. p. 200-4. (Pubitemid 41688257)
11. Obreja VVN. The reverse leakage current of present-day manufactured silicon PN junctions and their maximum permissible operation temperature. In: Proceedings 2005 international semiconductor device research symposium (ISDRS 2005). Bethesda (USA); 2005. p. 288-9.
12. V.V.N. Obreja On the leakage current of present-day manufactured semiconductor junctions Solid State Electron 49 1 2000 49 57 (Pubitemid 32213061)
13. V.V.N. Obreja An experimental investigation on the nature of reverse current of power silicon PN junctions IEEE Trans Electron Dev 49 2002 155 163 (Pubitemid 34504293)
14. Obreja VVN, Manea E, Codreanu C, Avram M, Podaru C. The junction edge leakage current and the blocking I-V characteristics of commercial glass passivated thyristor devices. In: Proceedings international semiconductor conference (CAS2005); 2005. p. 447-50. (Pubitemid 44867457)
15. Obreja VVN. Experimental drain I-V characteristics of power MOS transistors and the nature of reverse leakage current of oxide passivated PN junctions. In: Proceedings international semiconductor conference (CAS2005). p. 305-8.
16. Y. Wang, C.C. Zhu, and C.Y. Wu Improving reliability of beveled power semiconductor devices passivated by SIPOS Microelectron Reliab 45 2005 535 539 (Pubitemid 40415144)
17. Obreja VVN, Codreanu C. Experiments on behaviour of power silicon PN junctions under reverse bias voltage at high temperature. In: Proceedings EuroSIME2006 - thermal &mechanical simulation and experiments in microelectronics and microsystems; 2006. p. 107-12.
18. Obreja VVN. On the reliability of power silicon rectifier diodes above the maximum permissible operation junction temperature. In: Proceedings 2006 international symposium on industrial electronics (ISIE2006); 2006. p. 835-40.
19. B.J. Baliga High-voltage device termination techniques - a comparative review IEE Proc-I Commun Speech Vision 129 5 1982
20. H.J. Schulze, and R. Kuhnert Realization of a high voltage planar junction termination for power devices Solid State Electron 32 1989 175 176
21. Chao DS et al. Optimization and fabrication of planar edge termination techniques for a high breakdown voltage and low leakage current p-i-n diode. In: Proc 9th annual IEEE applied power electronics conference and exhibition (APEC04); 2004. p. 241-5.
22. V.A.K. Temple, and M.S. Adler Calculation of the diffusion curvature related avalanche breakdown in high-voltage planar P-N junctions IEEE Trans Electron Dev 22 1975 910 916
23. M. Bakowski, and K.I. Lundstrom Depletion layer characteristics at the surface of beveled high-voltage PN junctions IEEE Trans Electron Dev 20 1973 550 563
24. J. Cornu, S. Schweitzer, and O. Kuhn Double positive beveling: a better edge contour for high voltage devices IEEE Trans Electron Dev 21 1974 181 184
25. M.S. Adler, and V.A.K. Temple A general method for predicting the avalanche breakdown voltage of negative bevelled devices IEEE Trans Electron Dev 23 1976 956 960
26. V.A.K. Temple, and M.S. Adler The theory and application of a simple etch contour for near ideal breakdown voltage in plane and planar PN junctions IEEE Trans Electron Dev 23 1976 950 955
27. W. Tantraporn, and V.A.K. Temple Multiple-zone-mask junction termination extention - a high yield near ideal breakdown voltage technology IEEE Trans Electron Dev 34 1987 2200 2210 (Pubitemid 18521665)
28. R. Stengl, and E. Falck Surface breakdown and stability of high voltage planar junctions IEEE Trans Electron Dev 38 1991 2181 2188 (Pubitemid 21690782)
29. Obreja VVN. Influence of PN junction surface region upon the peak pulse power of silicon transient voltage suppressors. In: Proc international semiconductor conference (CAS1997); 1997. p. 331-334.
30. Obreja VVN. Investigation on operation of silicon power devices in the breakdown region of electrical characteristic. In: Proc international semiconductor conference (CAS 2001); 2001. p. 485-8.