Performance benchmarks for Si, III-V, TFET, and carbon nanotube FET - Re-thinking the technology assessment methodology for complementary logic applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Wei, Lan ^a   Oh, Saeroonter ^a   Wong, H S Philip ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CARBON NANOTUBE FET; CIRCUIT NOISE; COMPLEMENTARY LOGIC; DEVICE TECHNOLOGIES; DEVICE VARIATIONS; ENERGY-DELAY OPTIMIZATION; FREE VARIABLE; GATE LENGTH; NEW DEVICES; OFF-STATE CURRENT; OPTIMAL ENERGY; OPTIMAL SETS; SUPPLY VOLTAGES; TECHNOLOGY ASSESSMENTS;

BENCHMARKING; CARBON NANOTUBES; ELECTRON DEVICES; MESFET DEVICES; OPTIMIZATION; SILICON;

EQUIPMENT;

EID: 79951843158     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703373     Document Type: Conference Paper

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