Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Lu, Z ^a,b   Collaert, N ^a   Aoulaiche, M ^a   De Wachter, B ^a   De Keersgieter, A ^a   Fossum, J G ^b   Altimime, L ^a   Jurczak, M ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW VOLTAGES; MOSFETS; ON STATE CURRENT; ROOM TEMPERATURE; STANDARD CMOS; SUBTHRESHOLD SLOPE; ULTRA-THIN;

ELECTRON DEVICES;

EID: 79951834994     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703377     Document Type: Conference Paper

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