Metal-ferroelectric-metal-oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Rusu, Alexandru ^a   Salvatore, Giovanni A ^a   Jiménez, David ^b   Ionescu, Adrian M ^a  

^a EPFL   (Switzerland)

^b UNIVERSITAT AUTÒNOMA DE BARCELONA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC LAYER; GATE STACKS; HYSTERETIC CHARACTERISTICS; INTERNAL VOLTAGE; METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTORS; METAL-OXIDE; MINOR LOOP; MOS TRANSISTORS; NEGATIVE CAPACITANCE; NEGATIVE CAPACITANCE EFFECT; P-TYPE; ROOM TEMPERATURE; SUBTHRESHOLD SWING; TEST STRUCTURE;

CAPACITANCE; ELECTRON DEVICES; FERROELECTRICITY; FIELD EFFECT TRANSISTORS; LOGIC GATES; MESFET DEVICES; METALS; SILICON COMPOUNDS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

AMPLIFICATION;

EID: 79951832470     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703374     Document Type: Conference Paper

References (9)

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