Cohesion: An adaptive hybrid memory model for accelerators

IEEE Micro

Volumn 31, Issue 1, 2011, Pages 42-55

  Kelm, John H ^a   Johnson, Daniel R ^a   Tuohy, William ^a   Lumetta, Steven S ^a   Patel, Sanjay J ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Accelerator; cache coherence; computer architecture

Indexed keywords

ACCELERATOR; ADDRESS SPACE; CACHE COHERENCE; HYBRID MEMORIES; RUNTIMES; TEMPORAL DATA;

ADHESION;

COMPUTER ARCHITECTURE;

EID: 79951831804     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2011.8     Document Type: Article

References (11)

1. J.H. Kelm et al., "Cohesion: A Hybrid Mem-ory Model for Accelerators," Proc. 37th Ann. Int'l Symp. Computer Architecture, ACM Press, 2010, pp. 429-440.
2. S.V. Adve et al., "Comparison of Hardware and Software Cache Coherence Schemes," Sigarch ComputerArchitecture News, vol. 19, no. 3, 1991, pp. 298-308.
3. J.K. Bennett, J.B. Carter, and W. Zwaene-poel, "Munin: Distributed Shared Memory Based On Type-Specific Memory Coher-ence," Proc. 2ndACM Sigplan Symp. Princi-ples & Practice of Parallel Programming, ACM Press, 1990, pp. 168-176.
4. M.D. Hill et al., "Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors," ACM Trans. ComputerSystems,vol. 11, no. 4, 1993, pp. 300-318.
5. J.H. Kelm et al., "ATask-Centric Memory Model for Scalable Accelerator Architec-tures," Proc. 18th Int'l Conf. ParallelArchi-tectures and Compilation Techniques (Pact 09), IEEE CS Press, 2009, pp. 77-87.
6. L.M. Censier and P. Feautrier, "A New Solu-tion to Coherence Problems in Multicache Systems," IEEE Trans. Computers, vol. 27, no. 12, 1978, pp. 1112-1118. (Pubitemid 9404547)
7. L.A. Barroso et al., "Piranha: A Scalable Architecture Based on Single-Chip Multi-processing," Proc. 27th Ann. Int'l Symp. ComputerArchitecture, ACM Press, 2000, pp. 282-293.
8. M. Frigo, C.E. Leiserson, and K.H. Randall, "The Implementation of the Cilk-5 Multi-threaded Language," ACM Sigplan Notices, vol. 33, no. 5, 1998, pp. 212-223.
9. J. Reinders, Intel Threading Building Blocks: Outfitting C++ for Multi-Core Processor Parallelism, O'Reilly, 2007.
10. M. Gschwind, "Chip Multiprocessing and the Cell Broadband Engine," Proc. 3rd Conf. Computing Frontiers, ACM, 2006, pp. 1-8, doi:10.1145/1128022.1128023. (Pubitemid 46644666)
11. J.H. Kelm et al., "Rigel: An Architecture and Scalable Programming Interface for a 1000-Core Accelerator," Proc. 36th Ann. Int'l Symp. Computer Architecture, ACM Press, 2009, pp. 140-151.