Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Wang, Ching Hua ^a   Tsai, Yi Hung ^a   Lin, Kai Chun ^a   Chang, Meng Fan ^a   King, Ya Chin ^a   Lin, Chrong Jung ^a   Sheu, Shyh Shyuan ^b   Chen, Yu Sheng ^b   Lee, Heng Yuan ^b   Chen, Frederick T ^b   Tsai, Ming Jinn ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR JUNCTION TRANSISTOR; BIT LINES; CMOS COMPATIBLE; CMOS LOGIC; CURRENT DRIVERS; GATE LENGTH; HIGH GAIN; LOW VOLTAGES; MOSFETS; OXIDE THICKNESS; SELF-ALIGNED; STACKED FILM; WORDLINES;

ELECTRON DEVICES; THREE DIMENSIONAL; TITANIUM NITRIDE; TUNNEL DIODES;

BIPOLAR TRANSISTORS;

EID: 79951830138     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703446     Document Type: Conference Paper

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