Thermal stresses and deformations of Cu pillar flip chip BGA package: Analyses and measurements

International Microsystems Packaging Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference, Proceedings

Volumn , Issue , 2010, Pages

  Jhou, J R ^a   Tsai, M Y ^a   Wu, C Y ^b   Chen, K M ^b  

^a CHANG GUNG UNIVERSITY   (Taiwan)

^b UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Copper pillar bump; Finite element method; Flip chip; Moir interferometry; Stress; Thermal deformation; Warpage

Indexed keywords

COPPER PILLARS; FINITE ELEMENT; FLIP CHIP; THERMAL DEFORMATION; WARPAGES;

ALUMINUM; CHIP SCALE PACKAGES; COPPER; DEFORMATION; DIES; ELECTRONIC EQUIPMENT MANUFACTURE; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; INTERFEROMETRY; MICROSYSTEMS; STRESSES; THREE DIMENSIONAL;

PACKAGING;

EID: 79951662119     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMPACT.2010.5699597     Document Type: Conference Paper

References (7)

1. J. Kloeser, and E.-A. Weißbach, "High Performance Flip-Chip Packages with copper pillar bumping," Global SMT Packaging, pp. 28-31, May, 2006
2. K. M. Chen and T. S. Lin, "Copper Pillar Bump Design Optimization for Lead Free Flip-Chip Packaging," Journal of Materials Science: Materials in Electronics, vol. 21, no. 3, pp. 278-284, 2009
3. P. J. Cheng et al., "A Challenge of 45 nm Extreme Low-k Chip Using Cu Pillar Bump as 1st Interconnection," Electron. Compon. and Technol. Conf., 2010
4. J. M. G. Ong et al., "Optimization of the Thermomechanical Reliability of a 65 nm Cu/low-k Large-Die Flip Chip Package," IEEE Trans. on Compon. and Packag. Technol., 2009
5. D. Post, B. Han, and P. Ifju, "High Sensitivity Moiré: Experimental Analysis for Mechanics and Materials," New York: Springer-Verlag, 1994.
6. E. Suhir, "Die Attachment Design and Its Influence on Thermal Stresses in the Die and the Attachment," in Proc. 37th Electron. Compon. Conf. IEEE/EIA, pp. 508-517, 1987
7. M. Y. Tsai et al., "A Note on Suhir's Solution of Thermal Stresses for a Die-Substrate Assembly," J. Electron. Packag. vol 126, pp. 115-119, 2004