3D stacking DRAM using TSV technology and microbump interconnect

International Microsystems Packaging Assembly and Circuits Technology Conference, IMPACT 2010 and International 3D IC Conference, Proceedings

Volumn , Issue , 2010, Pages

  Chung, Kee Wei ^a   Shih, Steven ^a   Lu, Su Tsai ^b   Chen, Tai Hong ^b   Chen, Chwan Tyaw ^c   Ho, Jason ^a   Chen, Jen Jun ^a   Lin, Jeng Ping ^a  

^a NANYA TECHNOLOGY CORPORATION   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c Plating Technology Development Department   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; CHIP STACKING; CHIP STRENGTH; DRAM DEVICES; FINE PITCH; HIGH BANDWIDTH; HIGH DENSITY; KEY PROCESS; LOW POWER; MICRO-BUMPS; PERFORMANCE ENHANCEMENTS; PERFORMANCE REQUIREMENTS; PROCESS STEPS; THROUGH-SILICON-VIA; TRANSISTOR SCALING; WAFER THINNING;

MICROSYSTEMS; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL; TIN;

CHIP SCALE PACKAGES;

EID: 79951611577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMPACT.2010.5699629     Document Type: Conference Paper

References (10)

1. S.J. Koester et al., IBM J. Res. Dev., 2008, Vol.52, pp. 583-597
2. J.V. Olmen et al., International 3D System Integration Conference, 2009, pp.1-5.
3. M.Kawano et al., International Electron Devices Meeting, 2006, pp.1-4
4. S.Ramaswami et al., IEEE Transactions on Device and Materials Reliability, 2009, Vol4, pp.524-528
5. D.Y.Chen et al., International Electron Devices Meeting, 2009, p.p 353-356
6. R.Beica et al., Electronics Packaging Technology Conference, 2008, p.p 212-218.
7. S.Takyu et al., Electronics Packaging Technology Conference, 2008, p.p 1511-1516.
8. V.N.Sekhar et al., Electronics Packaging Technology Conference, 2008, p.p 1517-1524
9. S.W.Yoon et al., International 3D SystemIntegration Conference, 2009, p.p 1-5
10. S.Pozder et al., International Interconnect Technology Conference, 2007, p.p 213-215