Efficient custom instructions generation for system-level design

Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Volumn , Issue , 2010, Pages 445-448

  Huynh, Huynh Phung ^a   Liang, Yun ^b   Mitra, Tulika ^c  

^a INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

^b ADVANCED DIGITAL SCIENCES CENTER   (Singapore)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC; CRITICAL REGION; CUSTOM DESIGN; CUSTOM INSTRUCTION; CUSTOMIZABLE; CUSTOMIZABLE PROCESSORS; DESIGN-AUTOMATION TOOLS; EFFICIENT ALGORITHM; EMBEDDED PROCESSORS; GRAPH PARTITIONING; HIGH QUALITY; ITERATIVE SOLUTIONS; KEY COMPONENT; MULTI-LEVEL; PERFORMANCE BOTTLENECKS; PROCESSOR CORES; RAPID FEEDBACK; SOFTWARE SOLUTION; SOFTWARE SPECIFICATION; SYSTEM LEVEL DESIGN;

ALGORITHMS; COMPUTER AIDED DESIGN; EMBEDDED SOFTWARE; MULTIPROCESSING SYSTEMS;

AVAILABILITY;

EID: 79551521447     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2010.5681456     Document Type: Conference Paper

References (6)

1. L. N. Chakrapani et al. Languages and Compilers for High Performance Computing, chapter Trimran: An Infrastructure for Research in Instruction- Level Parallelism. 2005.
2. C. M. Fiduccia and R. M. Mattheyses. A linear-time heuristic for improving network partitions. In DAC, 1982.
3. H. P. Huynh and T. Mitra. Instruction-set customization for real-time embedded systems. In DATE, 2007.
4. G. Karypis and V. Kumar. Multilevel k-way partitioning scheme for irregular graphs. Journal of Parallel and Distributed Computing, 1998.
5. B. W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. The Bell System Technical Journal, 1970.
6. L. Pozzi, K. Atasu, and P. Ienne. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE TCAD, 25(7), July 2006.