Variation-aware task and communication mapping for MPSoC architecture

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 2, 2011, Pages 295-307

  Wang, Feng ^a   Chen, Yibo ^b   Nicopoulos, Chrysostomos ^c   Wu, Xiaoxia ^a   Xie, Yuan ^b   Vijaykrishnan, Narayanan ^b  

^a QUALCOMM INC   (United States)

^b The Pennsylvania State University   (United States)

^c UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

Multiprocessor system on chips (MPSoCs); process variability; scheduling; task mapping

Indexed keywords

COMMUNICATION LINKS; COMPUTATION METHODS; DEEP SUBMICROMETER; DESIGN HIERARCHY; ENTIRE SYSTEM; MAPPING ALGORITHMS; MAPPING METHODOLOGY; MAPPING SCHEME; MULTIPROCESSOR SYSTEM ON CHIPS; NETWORK ON CHIP; NEW DESIGN; PARADIGM SHIFTS; PARAMETER VARIATION; PERFORMANCE CONSTRAINTS; PROCESS VARIABILITY; PROCESS VARIATION; PROCESSING CORE; ROUTING PATH; STATISTICAL DESIGN; TASK MAPPING; TASK-SCHEDULING; YIELD IMPROVEMENT;

COMMUNICATION; COMPUTATIONAL EFFICIENCY; CONFORMAL MAPPING; DESIGN; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; TIMING JITTER; VLSI CIRCUITS;

MULTIPROCESSING SYSTEMS;

EID: 78951489090     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2077830     Document Type: Conference Paper

References (42)

1. S. Borkar, "Designing reliable systems from unreliable components: The challenges of transistor variability and degradation," IEEE Micro, vol. 25, no. 6, pp. 10-16, Nov.-Dec. 2005.
2. G. Martin and H. Chang, "Kluwer Academic Publishers was merged into Springer in 2004," Winning the SoC Revolution: Experiences in Real Design. Boston, MA: Kluwer, 2003.
3. T. Givargis, F. Vahid, and J. Henkel, "System-level exploration for pareto-optimal configurations in parameterized system-on-a-chip," IEEE Trans. VLSI Syst., vol. 10, no. 4, pp. 416-422, Aug. 2002.
4. A. Jerraya and W. Wolf, Multiprocessor Systems-on-Chips. San Mateo, CA: Morgan Kaufmann, 2005.
5. W. J. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. 38th Des. Automat. Conf., Jun. 2001, pp. 684-689.
6. L. Benini and G. D. Micheli, "Networks on chips: A new SoC paradigm," IEEE Comput., vol. 35, no. 1, pp. 70-78, Jan. 2002.
7. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in Proc. Des. Automat. Conf., 2003, pp. 338-342.
8. J. Hu and R. Marculescu, "Exploiting the routing flexibility for energy/ performance aware mapping of regular NoC architectures," in Proc. DATE, vol. 1. 2003, p. 10688.
9. K. Ramamritham, "Allocation and scheduling of precedence-related periodic tasks," IEEE Trans. Parallel Distributed Syst., vol. 6, no. 4, pp. 412-420, Apr. 1995.
10. G. C. Sih and E. A. Lee, "A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures," IEEE Trans. Parallel Distributed Syst., vol. 4, no. 2, pp. 175-187, Feb. 1993.
11. W. H. Wolf, "An architectural co-synthesis algorithm for distributed, embedded computing systems," IEEE Trans. Very Large Scale Integr. Syst., vol. 5, no. 2, pp. 218-229, Jun. 1997.
12. Y. Zhang, X. Hu, and D. Z. Chen, "Task scheduling and voltage selection for energy minimization," in Proc. Des. Automat. Conf., 2002, pp. 183- 188.
13. L. Jiong and N. Jha, "Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems," in Proc. 7th Asia South Pacific Des. Automat. Conf., 2002, pp. 719-726.
14. J. Liu, P. Chou, N. Bagherzadeh, and F. Kurdahi, "Power-aware scheduling under timing constraints for mission-critical embedded systems," in Proc. 38th Conf. Des. Automat., 2001, pp. 840-845.
15. L. Shang and N. K. Jha, "Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs," in Proc. Conf. Asia South Pacific Des. Automat./VLSI Des., Jan. 2002, pp. 345-352.
16. J. Hu and R. Marculescu, "Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints," in Proc. Des. Automat. Test Eur. Conf., 2004, pp. 234-239.
17. D. Atienza, P. Meloni, S. Carta, L. Benini, G. De Micheli, L. Raffo, and S. Murali, "Synthesis of predictable networks-on-chip-based interconnect architectures for chip multiprocessors," IEEE Trans. VLSI Syst., vol. 15, no. 8, pp. 869-880, Aug. 2007.
18. D. Atienza and E. Martinez, "Inducing thermal-awareness in multicore systems using networks-on-chip," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, May 2009, pp. 187-192.
19. C. Hongliang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single pert-like traversal," in Proc. Int. Conf. Comput.-Aided Des., 2003, pp. 621-625.
20. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with spatial correlations," in Proc. Int. Conf. Comput.-Aided Des., 2003, pp. 900-907.
21. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis," in Proc. DAC, Jun. 2004, pp. 331-336.
22. D. Sinha, N. V. Shenoy, and H. Zhou, "Statistical gate sizing for timing yield optimization," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2005, pp. 1037-1041.
23. M. R. Guthaus, N. Venkateswarant, C. Visweswariaht, and V. Zolotov, "Gate sizing using incremental parameterized statistical timing analysis," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 2005, pp. 1029- 1036.
24. K. Chopra, S. Shah, A. Srivastava, D. Blaauw, and D. Sylvester, "Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2005, pp. 1023-1028.
25. V. Khandelwal, A. Davoodi, A. Nanavati, and A. Srivastava, "A probabilistic approach to buffer insertion," in Proc. ICCAD, 2003, pp. 560- 567.
26. A. K. Singh, M. Mani, and M. Orshansky, "Statistical technology mapping for parametric yield," in Proc. ICCAD, 2005, pp. 511-518.
27. S. Garg and D. Marculescu, "System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs," in Proc. IEEE DATE, Apr. 2007, pp. 1-6.
28. D. Marculescu and S. Garg, "System-level process-driven variability analysis for single and multiple voltage-frequency island systems," in Proc. IEEE/ACM ICCAD, Nov. 2006, pp. 541-546.
29. K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of die-to-die and within die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," J. Solid-State Circuits, vol. 37, no. 2, pp. 183-190, Feb. 2002.
30. T. S. Tia, Z. Deng, M. Shankar, M. Storch, J. Sun, L. C. Wu, and J. W. S. Liu, "Probabilistic performance guarantee for real-time tasks with varying computation times," in Proc. Real-Time Technol. Applicat. Symp., 1995, pp. 164-173.
31. X. S. Hu, Z. Tao, and E. H. M. Sha, "Estimating probabilistic timing performance for real-time embedded systems," IEEE Trans. VLSI Syst., vol. 9, no. 6, pp. 833-844, Dec. 2001.
32. G. D. Veciana, M. F. Jacome, and J.-H. Guo, "Hierarchical algorithms for assessing probabilistic constraints on system performance," in Proc. IEEE/ACM DAC, 1998, pp. 251-256.
33. C. Clark, "The greatest of a finite set of random variables," Oper. Res., vol. 9, no. 2, pp. 145-162, Mar.-Apr. 1961.
34. H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in Proc. IEEE/ACM ICCAD, Nov. 2003, pp. 621-625.
35. H. Koh and H. Chuang, "Finding a minimal set of base paths of a program," Int. J. Comput. Inform. Sci., vol. 8, no. 6, pp. 473-489, 1979.
36. H. Koh, "Flow network reduction for unique topological ordering," in Proc. ACM Annu. Comput. Sci. Conf., 1989, pp. 335-338.
37. G. M. Chiu, "The odd-even turn model for adaptive routing," IEEE Trans. Parallel Distributed Syst., vol. 11, no. 7, pp. 729-738, Jul. 2000.
38. Y. B. Li and J. Henkel, "A framework for estimation and minimizing energy dissipation of embedded HW/SW systems," in Proc. DAC, 1998, pp. 188-193.
39. R. P. Dick. (2003). Embedded Systems Synthesis Benchmarks Suite (e3s) [Online]. Available: http://www.ece.northwestern.edu/ dickrp/e3s
40. Y. Xie and W.-L. Hung, "Temperature-aware task allocation and scheduling for embedded multiprocessor systems-on-chip (MPSoC) design," J. VLSI Signal Process. Syst., vol. 45, no. 3, pp. 177-189, 2006.
41. S. Jin, G. Schiavone, and D. Turgut, "A performance study of multiprocessor task scheduling algorithms," J. Supercomput., vol. 43, no. 1, pp. 77-97, 2008.
42. E. R. Altman, V. K. Agarwal, G. R. Gao, and G. Liao, "A comparative study of multiprocessor list scheduling heuristics," in Proc. 27th Hawaii Int. Conf. Syst. Sci. Architect., vol. 1. Jan. 1994, pp. 68-77.