An FPGA implementation of a brushless DC motor speed controller

2010 IEEE 16th International Symposium for Design and Technology of Electronics Packages, SIITME 2010

Volumn , Issue , 2010, Pages 99-102

  Alecsa, Bogdan ^a   Onea, Alexandru ^a  

^a GHEORGHE ASACHI TECHNICAL UNIVERSITY OF IASI   (Romania)

Author keywords

BLDC; FPGA; Speed control; System generator

Indexed keywords

BLDC; BRUSHLESS DC; CONTROLLER DESIGNS; DIGITAL CONTROLLERS; EXPERIMENTAL TESTING; FPGA; FPGA IMPLEMENTATIONS; LOGIC SIMULATIONS; LOW COSTS; MOTOR CONTROL; SYSTEM GENERATOR;

BRUSHLESS DC MOTORS; DC MOTORS; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SPEED CONTROL; SPEED REGULATORS;

CONTROLLERS;

EID: 78751545425     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIITME.2010.5653617     Document Type: Conference Paper

References (6)

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4. A. Emadi, Handbook of Automotive Power Electronics and Motor Drives, CRC Press, 2005.
5. A. Sathyan, N. Milivojevic, Y.-J. Lee, M. Krishnamurthy, A. Emadi, "An FPGA-based novel digital PWM control scheme for BLDC motor drives", IEEE Transactions on Industrial Electronics, vol. 56, no. 8, August 2009.
6. B. Alecsa, A. Onea, "An FPGA implementation of the time domain deadbeat algorithm for control applications", Proceedings of 2009 Norchip, Trondheim, Norway, November 2009.