Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Volumn , Issue , 2010, Pages 37-40

  Numata, Toshinori ^a   Saitoh, Masumi ^a   Nakabayashi, Yukio ^a   Ota, Kensuke ^a   Uchida, Ken ^b  

^a TOSHIBA CORPORATION   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPRESSIVE STRAIN; MOBILITY ENHANCEMENT; PARASITIC CAPACITANCE; PARASITIC RESISTANCES; POLY-SI GATES; RAISED SOURCE/DRAIN; SI NANOWIRE; STRAIN EFFECT; STRAINED SILICON CHANNEL; STRESS-INDUCED; THIN SPACER;

NANOWIRES; POLYSILICON;

INTEGRATED CIRCUITS;

EID: 78751502445     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2010.5667859     Document Type: Conference Paper

References (9)

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8. Y. Nakabayashi et al., to be presented at SSDM 2010
9. A. F. Willoughby, "Double-Diffusion Process in Silicon" in F. F. Y. Wang, Ed., Impurity Doping Process in Silicon (1981).