XFCB: A high speed complementary bipolar process on bonded SOI

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn 1992-October, Issue , 1992, Pages 264-267

  Feindt, S ^a   Hajjar, J J J ^a   Lapham, J ^a   Buss, D ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CUTOFF FREQUENCY; POLYCRYSTALLINE MATERIALS; POLYSILICON; SILICON WAFERS; WAFER BONDING;

COMPLEMENTARY BIPOLAR; COMPLEMENTARY BIPOLAR PROCESS; DEEP TRENCH ISOLATION; DIRECT WAFER BONDING; FABRICATION PROCESS; PNP TRANSISTORS; SINGLE LAYER; TRANSISTOR TYPES;

TRANSISTORS;

EID: 78651409257     PISSN: 10889299     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BIPOL.1992.274036     Document Type: Conference Paper

References (9)

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3. J. Lapham, B. Scharf and R. Payne, "A Complementary Bipolar Process for High Speed Precision Linear Circuits", Proc. IEEE Bipolar Circuit and Technology Meeting, p. 31, 1986
4. S. Gaul, J. Delgado, G. Rouse & C. McLachlan, "A Full Dielectri-cally Isolated Complementary Bipolar Process Using Bonded Wafers", Proc. of the IEEE SOSISOl workshop, p. 72, 1987
5. Proceeding of the 4th International Symposium on Silicon-on-Insulator Technology and Devices, D.N. Schmidt ed., May 1990, Montreal, The electrochemical Society, NJ
6. T. Abe, M. Nakano and T. Itoh, " Silicon Wafer-Bonding Process Technology for SOI Structures", Proceeding of the 4th International Symposium on Silicon-on-Insulator Technology and Devices, D.N. Schmidt ed., May 1990, Montreal, The Electrochemical Society, NJ
7. A. Hayasaka, Y. Tamaki, M. Kawamura, K. Ogiue and S. Ohwaki, "U-Groove Isolation Technique for High Speed Bipolar VLSI's", IEDM Techn. Digest, p. 62, 1982.
8. C.W. Teng, C. Slawinski and W.R. Hunter, "Defect Generation in Trench Isolation", IEDM Techn. Digest, p. 586, 1984.
9. Shin-Etsu Handotai Co., Ltd., Tokyo, Japan