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Volumn , Issue , 2010, Pages 90-96

Process variation aware transcoding for low power H.264 decoding

Author keywords

H.264; Low power; Process variation; SRAM; Transcoding

Indexed keywords

H.264; LOW POWER; PROCESS VARIATION; SRAM; TRANSCODING;

EID: 78651406324     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTMED.2010.5666988     Document Type: Conference Paper
Times cited : (4)

References (22)
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  • 14
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    • A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM or Feb.
    • A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM or Nishikawa, T. et al., "A 60MHz 240mW MPEG-4 Video-Phone LSI with 16Mb Embedded DRAM," ISSCC Digest of Technical Papers, pp.230-231, Feb. 2000.
    • (2000) ISSCC Digest of Technical Papers , pp. 230-231
    • Nishikawa, T.1
  • 17
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    • A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors
    • I. J. Chang, D. Mohapatra, K. Roy, "A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors," DAC 2009, pp. 670-675
    • DAC 2009 , pp. 670-675
    • Chang, I.J.1    Mohapatra, D.2    Roy, K.3
  • 19
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    • Series on Integrated Circuits and Systems
    • New York, NY: Springer New York
    • J. M. Rabaey, Low Power Design Essentials, Series on Integrated Circuits and Systems, New York, NY: Springer New York, 2009.
    • (2009) Low Power Design Essentials
    • Rabaey, J.M.1
  • 22
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    • The impact of intrinsic device fluctuations on CMOS SRAM cell stability
    • Apr.
    • A. Bhavanagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
    • (2001) IEEE J. Solid State Circuits , vol.36 , Issue.4 , pp. 658-665
    • Bhavanagarwala, A.1    Tang, X.2    Meindl, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.