Multi-Gbit I/O and interconnect Co-design for power efficient links

2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010

Volumn , Issue , 2010, Pages 1-4

  Jaussi, James E ^a   Leddige, Mike ^a   Horine, Bryce ^a   O'Mahony, Frank ^a   Casper, Bryan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Area array connectors; Flex; HDI; Micro twinax cable; Power efficient I O; Top of the package interconnects

Indexed keywords

CABLES; ELECTRONICS PACKAGING; LIQUID CRYSTAL POLYMERS; NONVOLATILE STORAGE;

CMOS TRANSCEIVERS; FLEX; HIGH DENSITY INTERCONNECTS; ON-DIE TRANSMISSION LINES; PACKAGE INTERCONNECTS; PARALLEL LINKS; POWER EFFICIENCY; POWER EFFICIENT;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 78650959809     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2010.5642529     Document Type: Conference Paper

References (8)

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8. B. Casper, et al., "Future microprocessor interfaces: analysis, design and optimization." IEEE Custom Integrated Circuits conference, Sept. 2007, pp. 479-486.