-
1
-
-
77952123736
-
A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS
-
J. Howard, S. Dighe, Y. Hoskote et al.: "A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS"; In Proc. ofIEEE International Solid-State Circuits Conference (ISSCC 2010), San Francisco, CA, USA, Feb. 2010.
-
Proc. OfIEEE International Solid-State Circuits Conference (ISSCC 2010), San Francisco, CA, USA, Feb. 2010
-
-
Howard, J.1
Dighe, S.2
Hoskote, Y.3
-
2
-
-
0003604496
-
A Message-Passing Interface Standard
-
MPI: Version 2.2, Available at
-
MPI: A Message-Passing Interface Standard, Version 2.2, Message Passing Interface Forum, Sept. 4, 2009. Available at: www.mpi-forum. org
-
Message Passing Interface Forum, Sept. 4, 2009
-
-
-
3
-
-
35048884271
-
Open MPI: Goals, Concept, and Design of a Next Generation MPI Implementation
-
Sept.
-
E. Gabriel, G.E. Fagg, G. Bosilca, T. Angskun, J.J. Dongarra, J.M.Squyres, V. Sahay, P. Kambadur, B. Barrett, A. Lumsdaine, R.H. Castain, D.J. Daniel, R.L. Graham, T.S. Woodall: "Open MPI: Goals, Concept, and Design of a Next Generation MPI Implementation"; In Proc. of 11th European PVM/MPI Users' Group Meeting, Budapest, Hungary, pp. 97-104, Sept. 2004.
-
(2004)
Proc. of 11th European PVM/MPI Users' Group Meeting, Budapest, Hungary
, pp. 97-104
-
-
Gabriel, E.1
Fagg, G.E.2
Bosilca, G.3
Angskun, T.4
Dongarra, J.J.5
Squyres, J.M.6
Sahay, V.7
Kambadur, P.8
Barrett, B.9
Lumsdaine, A.10
Castain, R.H.11
Daniel, D.J.12
Graham, R.L.13
Woodall, T.S.14
-
4
-
-
46049104179
-
Open MPI: A High Performance, Heterogenous MPI
-
R. L. Graham, G. M. Shipman, B. W. Barrett, R. H. Castain, G. Bosilca, A. Lumsdaine: "Open MPI: A High Performance, Heterogenous MPI"; In Proc. of Fifth International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks, Barcelona, Spain, September 2006.
-
Proc. of Fifth International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks, Barcelona, Spain, September 2006
-
-
Graham, R.L.1
Shipman, G.M.2
Barrett, B.W.3
Castain, R.H.4
Bosilca, G.5
Lumsdaine, A.6
-
7
-
-
62349093266
-
SoC-MPI: A flexible Message Passing Library for Multiprocessor Systems-on-Chips
-
P. Mahr, C. Lörchner, H. Ishebabi, C. Bobda: "SoC-MPI: A flexible Message Passing Library for Multiprocessor Systems-on-Chips"; In Proc. of IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig'08), Cancun, Mexico, December 2008.
-
Proc. of IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig'08), Cancun, Mexico, December 2008
-
-
Mahr, P.1
Lörchner, C.2
Ishebabi, H.3
Bobda, C.4
-
8
-
-
77954059823
-
High Performance Reconfigurable Multi-Processor-Based Computing on FPGAs
-
D. Göhringer, J. Becker: "High Performance Reconfigurable Multi-Processor-Based Computing on FPGAs"; In Proc. of IEEE International Parallel and Distributed Processing Symposium (IPDPS 2010), Atlanta, USA, April, 2010.
-
Proc. of IEEE International Parallel and Distributed Processing Symposium (IPDPS 2010), Atlanta, USA, April, 2010
-
-
Göhringer, D.1
Becker, J.2
-
9
-
-
70449884159
-
Star-wheels Network-on-chip Featuring a Self-adaptive Mixed Topology and a Synergy of a Circuit- and a Packet-switching Communication Protocol
-
D. Göhringer, B. Liu, M. Hübner, J. Becker: "STAR-WHEELS NETWORK-ON-CHIP FEATURING A SELF-ADAPTIVE MIXED TOPOLOGY AND A SYNERGY OF A CIRCUIT- AND A PACKET-SWITCHING COMMUNICATION PROTOCOL"; International Conference on Field Programmable Logic and Applications (FPL 2009), Prague, Czech Republic, September 2009.
-
International Conference on Field Programmable Logic and Applications (FPL 2009), Prague, Czech Republic, September 2009
-
-
Göhringer, D.1
Liu, B.2
Hübner, M.3
Becker, J.4
-
10
-
-
77954080043
-
CAPOS: Operating System for Runtime Scheduling, Task Mapping and Resource Management on Reconfigurable Multiprocessor Architectures
-
D. Göhringer, M. Hübner, E. Nguepi Zeutebouo, J. Becker: "CAPOS: Operating System for Runtime Scheduling, Task Mapping and Resource Management on Reconfigurable Multiprocessor Architectures"; In Proc. of Reconfigurable Architectures Workshop (RAW 2010) der IPDPS Konferenz, Atlanta, USA, April, 2010.
-
Proc. of Reconfigurable Architectures Workshop (RAW 2010) der IPDPS Konferenz, Atlanta, USA, April, 2010
-
-
Göhringer, D.1
Hübner, M.2
Nguepi Zeutebouo, E.3
Becker, J.4
-
11
-
-
77954279320
-
A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip
-
D. Göhringer, M. Hübner, M. Benz, J. Becker: "A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip"; Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010),Charlotte, USA, May, 2010.
-
Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010),Charlotte, USA, May, 2010
-
-
Göhringer, D.1
Hübner, M.2
Benz, M.3
Becker, J.4
-
12
-
-
21244433563
-
Spidergon: A novel on-chip communication network
-
M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra: "Spidergon: a novel on-chip communication network"; In Proc. of Intern. Symposium on SoC, Nov. 2004.
-
Proc. of Intern. Symposium on SoC, Nov. 2004
-
-
Coppola, M.1
Locatelli, R.2
Maruccia, G.3
Pieralisi, L.4
Scandurra, A.5
-
14
-
-
39749119355
-
A parallel strategy for biological sequence alignment in restricted memory space
-
R. B. Batista, A. Boukerche, A. C. M. A. de Melo: "A parallel strategy for biological sequence alignment in restricted memory space"; Journal of Parallel and Distributed Processing, vol. 68, no. 4, pages 548-561, 2008..
-
(2008)
Journal of Parallel and Distributed Processing
, vol.68
, Issue.4
, pp. 548-561
-
-
Batista, R.B.1
Boukerche, A.2
De Melo, A.C.M.A.3
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