Analog operation of junctionless transistors at cryogenic temperatures

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2010, Pages

  Doria, R T ^a   Pavanello, M A ^a,b   Trevisoli, R D ^a   De Souza, M ^b   Lee, C W ^c   Ferain, I ^c   Dehdashti Akhavan, N ^c   Yan, R ^c   Razavi, P ^c   Yu, R ^c   Kranti, A ^c   Colinge, J P ^c  

^a UNIVERSITY OF SÃO PAULO   (Brazil)

^b CENTRO UNIVERSITÁRIO DA FEI   (Brazil)

^c UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 78650584145     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2010.5641393     Document Type: Conference Paper

References (9)

1. ITRS roadmap, 2007 edition. http://public.itrs.net.
2. J.P. Colinge et al., Nature Nanotechnology, 5(3), 225(2010).
3. C.W. Lee et al., Solid-State Electronics, 54(2), 97(2010).
4. R.T. Doria et al., in: Proceedings EuroSOI 2010, 79(2010).
5. C.W. Lee et al., IEEE Trans. on Elect. Devices, 57(3), (2010).
6. J.P. Colinge et al., Proc. IEEE Intl SOI Conference, 1-2(2009).
7. E. A. Gutierrez et al., Low Temperature Electronics: Physics, Dev., Circ. and Applications, Academic Pres, 2001.
8. M.A. Pavanello et al., Cryogenics, 49, 590(2009).
9. M.A. Pavanello et al., Solid-State Electr., 52(12), 1904(2008).