A novel architecture for a massively parallel low level vision processing engine on chip

IEEE International Symposium on Industrial Electronics

Volumn , Issue , 2010, Pages 3033-3039

  Tomasi, Matteo ^a   Vanegas, Mauricio ^a,b   Barranco, Francisco ^a   Díaz, Javier ^a   Ros, Eduardo ^a  

^a UNIVERSITY OF GRANADA   (Spain)

^b UNIVERSIDAD PONTIFICIA BOLIVARIANA   (Colombia)

Author keywords

[No Author keywords available]

Indexed keywords

DESCRIPTORS; DESIGNING TECHNIQUES; FPGA-BASED IMPLEMENTATION; FRAMES PER SECONDS; HARDWARE DESIGN; HARDWARE RESOURCES; HARMONIC FILTER; LOCAL CONTRAST; LOCAL ORIENTATIONS; LOW-LEVEL VISION; MULTIPLE PROCESSING; MULTISCALES; NOVEL ARCHITECTURE; ON CHIPS; PROCESS INPUTS; PROCESSING ELEMENTS; PROCESSING ENGINE; RUNNING-IN; VISUAL FEATURE;

FEATURE EXTRACTION; INDUSTRIAL ELECTRONICS; RECONFIGURABLE HARDWARE;

OPTICAL FLOWS;

EID: 78650321727     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISIE.2010.5637211     Document Type: Conference Paper

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