A SystemC AMS model of an I2C bus controller

Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

Volumn , Issue , 2006, Pages 154-158

  Alassir, M ^a   Denoulet, J ^a   Romain, O ^a   Garda, P ^a  

^a SORBONNE UNIVERSITÉ   (France)

Author keywords

I2C controller; Model; Simulation; SystemC AMS

Indexed keywords

ANALOG BLOCKS; BUS INTERFACES; BUS PROTOCOL; CONTROL MODES; EXTERNAL ENVIRONMENTS; I2C CONTROLLER; INTEGRATED CONTROLLERS; INTERFACE CONTROLLERS; PACKET STRUCTURE; SIMULATION; SIMULATION RESULT; SYSTEM ON A CHIP; SYSTEMC; SYSTEMC-AMS; TIMING CONSTRAINTS;

BUSES; CONTROLLERS; DESIGN; INTEGRATED CONTROL; INTERNET PROTOCOLS; NANOSTRUCTURED MATERIALS; TIMING CIRCUITS;

COMPUTER SIMULATION;

EID: 78650312722     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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