메뉴 건너뛰기




Volumn , Issue , 2010, Pages 57-60

325GHz CPW band pass filter integrated in advanced HR SOI RF CMOS technology

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT GAINS; ELECTRIC SIMULATION; HIGH RESISTIVITY; MAXIMUM OSCILLATION FREQUENCY; NANOMETRICS; ON CHIPS; PASSIVE CIRCUITS; PASSIVE INTEGRATION; RF CMOS TECHNOLOGY; RF-CMOS; SIGE HBTS; STATE-OF-THE-ART PERFORMANCE; STMICROELECTRONICS;

EID: 78650052784     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (16)
  • 1
    • 34748828251 scopus 로고    scopus 로고
    • High frequency low noise potentialities of down to 65nm technology nodes MOSFETs
    • G. Dambrine et al., "High frequency low noise potentialities of down to 65nm technology nodes MOSFETs", IEEE GaAs Symposium, 2005.
    • (2005) IEEE GaAs Symposium
    • Dambrine, G.1
  • 4
  • 6
    • 33749260837 scopus 로고    scopus 로고
    • J. S. Rieh et al., in IEEE RFIC, pp. 395-398, 2004.
    • (2004) IEEE RFIC , pp. 395-398
    • Rieh, J.S.1
  • 9
  • 11
    • 34748865219 scopus 로고    scopus 로고
    • CMOS High Resistivity SOI: A promising technology for the integration of millimeter wave applications on silison
    • F. Gianesello et al., "CMOS High Resistivity SOI: a promising technology for the integration of millimeter wave applications on silison ", in Proc. MINT, 2006, pp. 99-104.
    • (2006) Proc. MINT , pp. 99-104
    • Gianesello, F.1
  • 12
    • 34748815024 scopus 로고    scopus 로고
    • 1, 8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS Technology
    • Hawaï, June
    • F. Gianesello et al., "1, 8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS Technology", IEEE MTT-S, Hawaï, June 2007.
    • (2007) IEEE MTT-S
    • Gianesello, F.1
  • 14
    • 34250346954 scopus 로고    scopus 로고
    • 65 nm RFCMOS technologies with bulk and HR SOI substrate for millimeter wave passives and circuits characterized up to 220 GHz
    • San Francisco, June, (to be published)
    • F. Gianesello et al., "65 nm RFCMOS technologies with bulk and HR SOI substrate for millimeter wave passives and circuits characterized up to 220 GHz", IEEE MTT-S, San Francisco, June 2006 (to be published).
    • (2006) IEEE MTT-S
    • Gianesello, F.1
  • 15
    • 27644494535 scopus 로고    scopus 로고
    • Silicon integrated dipole antennas on standard BiCMOS back-end process for 40-80 GHz applications
    • November
    • S. Montusclat et al., "Silicon integrated dipole antennas on standard BiCMOS back-end process for 40-80 GHz applications," JINA 2004. pp. 1721-1724, November 2004.
    • (2004) JINA 2004 , pp. 1721-1724
    • Montusclat, S.1
  • 16
    • 34748832040 scopus 로고    scopus 로고
    • Silicon integrated antenna development up to 80 GHz for millimeter wave wireless links
    • S. Montusclat et al., "Silicon integrated antenna development up to 80 GHz for millimeter wave wireless links", IEEE EuMW05.
    • IEEE EuMW05
    • Montusclat, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.