Sub-melt laser annealing followed by low-temperature RTP for minimized diffusion

Proceedings of the International Conference on Ion Implantation Technology

Volumn , Issue , 2000, Pages 167-170

  Felch, S B ^a   Downey, D E ^a   Arevalo, E A ^a   Talwar, S ^b   Gelatos, C ^b   Wang, Y ^b  

^a Varian Semiconductor Equipment Associates Inc   (United States)

^b Verdant Technologies   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALLINE DAMAGE; DOPANT ACTIVATION; IMPLANTED WAFERS; LASER ENERGY DENSITY; LOW TEMPERATURES; LOW-LEAKAGE CURRENT; MELTING THRESHOLD; RAPID THERMAL ANNEAL; SIMS PROFILE; SUB-MELT LASER ANNEALING; TWO-STEP PROCESS; WAFER TEMPERATURE;

DIFFUSION; DOPING (ADDITIVES); ELECTRIC RESISTANCE; ION IMPLANTATION; LEAKAGE CURRENTS; MELTING; RAPID THERMAL ANNEALING; RAPID THERMAL PROCESSING; SHEET RESISTANCE; THERMAL DIFFUSION IN LIQUIDS;

SILICON WAFERS;

EID: 78649821141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2000.924116     Document Type: Conference Paper

References (3)

1. International Technology Roadmap for Semiconductors, San lose: Semiconductor Industry Association, 1999.
2. S. Talwar, S. Felch, D. Downey, and Y. Wang, "Study of Laser Thermal Processing (LTP) to Meet sub-130nm Node Shallow Junction Requirements," these Proceedings.
3. B. Murto, "Recent Advances and Continuing Challenges in Ultra-Shallow Junctions," Proc. of Third National Implant Users Meeting, Oct. 21, 1999.