Efficient architecture and implementations of AES

ICACTE 2010 - 2010 3rd International Conference on Advanced Computer Theory and Engineering, Proceedings

Volumn 6, Issue , 2010, Pages

  Chen, Dong ^a   Shou, Guochu ^a   Hu, Yihong ^a   Guo, Zhigang ^a  

^a BEIJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS   (China)

Author keywords

AES; FPGA; KeyExpansion; Sub pipelined

Indexed keywords

EID: 78149323444     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICACTE.2010.5579818     Document Type: Conference Paper

References (11)

1. National Institute of Standards and Technology (NIST), "Advanced Encryption Standard (AES)".Federal Information Processing Standards (FIPS) Publication 197 ,November 2001.
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8. J. Zambreno, D. Nguyen, and A Choudhary, "Exploring area/delay tradeoffs in an AES FPGA implementation". FPL 2004, Antwerp, Belgium, 2004, (Lect. Notes Comput. Sci , 3203), pp. 575-585.
9. T. Good, and M. Benaissa, "Pipelined AES on FPGA with Support for Feedback Modes (in a Multi-channel Environment)". lET Information Security, vol. 1, no. 1, Mar. 2007, pp. 1-10.
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11. Rijmen, V., "Efficient implementation of the Rijndael S-box". http://wwwiaik.tugraz.ac.at/research/krypto/ AES/old/ Jijmen/rijndael/sbox.pdf