DAFT: Decoupled acyclic fault tolerance

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2010, Pages 87-97

  Zhang, Yun ^a   Lee, Jae W ^b   Johnson, Nick P ^a   August, David I ^a  

^a Princeton University   (United States)

^b Parakinetics Inc   (United States)

Author keywords

multicore; speculation; transient fault

Indexed keywords

FAULT TOLERANCE; MULTICORE PROGRAMMING; MULTITASKING; PARALLEL ARCHITECTURES;

HARDWARE EXTENSION; MULTI CORE; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; REDUNDANT MULTITHREADING; SPECULATION; TRANSIENT FAULTS; TRANSIENT-FAULT DETECTION;

FAULT DETECTION;

EID: 78149269828     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1854273.1854289     Document Type: Conference Paper

References (21)

1. E. D. Berger and B. G. Zorn. Diehard: Probabilistic memory safety for unsafe languages. In Proceedings of the ACM SIGPLAN '06 Conference on Programming Language Design and Implementation, June 2006.
2. S. S. Brilliant, J. C. Knight, and N. G. Leveson. Analysis of faults in an n-version software experiment. IEEE Trans. Softw. Eng., 16(2):238-247, 1990.
3. M. Gomaa, C. Scarbrough, T. N. Vijaykumar, and I. Pomeranz. Transient-fault recovery for chip multiprocessors. In Proceedings of the 30th annual international symposium on Computer architecture, pages 98-109. ACM Press, 2003.
4. R. W. Horst, R. L. Harris, and R. L. Jardine. Multiple instruction issue in the NonStop Cyclone processor. In Proceedings of the 17th International Symposium on Computer Architecture, pages 216-226, May 1990.
5. C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO '04: Proceedings of the International Symposium on Code Generation and Optimization, page 75, Washington, DC, USA, 2004. IEEE Computer Society.
6. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, PLDI '05, pages 190-200, New York, NY, USA, 2005. ACM.
7. A. Mahmood and E. J. McCluskey. Concurrent error detection using watchdog processors-a survey. IEEE Transactions on Computers, 37(2):160-174, 1988.
8. S. E. Michalak, K. W. Harris, N. W. Hengartner, B. E. Takala, and S. A. Wender. Predicting the number of fatal soft errors in los alamos national labratory's ASC Q computer. IEEE Transactions on Device and Materials Reliability, 5(3):329-335, September 2005.
9. S. S. Mukherjee, M. Kontz, and S. K. Reinhardt. Detailed design and evaluation of redundant multithreading alternatives. SIGARCH Comput. Archit. News, 30(2):99-110, 2002.
10. G. Novark, E. D. Berger, and B. G. Zorn. Exterminator: automatically correcting memory errors with high probability. In PLDI '07: Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation, pages 1-11, New York, NY, USA, 2007. ACM.
11. S. K. Reinhardt and S. S. Mukherjee. Transient fault detection via simultaneous multithreading. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 25-36. ACM Press, 2000.
12. G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, and D. I. August. SWIFT: Software implemented fault tolerance. In Proceedings of the 3rd International Symposium on Code Generation and Optimization, March 2005.
13. G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, D. I. August, and S. S. Mukherjee. Design and evaluation of hybrid fault-detection systems. In Proceedings of the 32th Annual International Symposium on Computer Architecture, pages 148-159, June 2005.
14. E. Rotenberg. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, page 84. IEEE Computer Society, 1999.
15. A. Shye, T. Moseley, V. J. Reddi, J. B. t, and D. A. Connors. Using process-level redundancy to exploit multiple cores for transient fault tolerance. Dependable Systems and Networks, International Conference on, 0:297-306, 2007.
16. T. J. Slegel, R. M. Averill III, M. A. Check, B. C. Giamei, B. W. Krumm, C. A. Krygowski, W. H. Li, J. S. Liptay, J. D. MacDougall, T. J. McPherson, J. A. Navarro, E. M. Schwarz, K. Shum, and C. F. Webb. IBM's S/390 G5 Microprocessor design. In IEEE Micro, volume 19, pages 12-23, March 1999.
17. N. Vachharajani, R. Rangan, E. Raman, M. J. Bridges, G. Ottoni, and D. I. August. Speculative decoupled software pipelining. In PACT '07: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, pages 49-59, Washington, DC, USA, 2007. IEEE Computer Society.
18. D. Walker, L. Mackey, J. Ligatti, G. A. Reis, and D. I. August. Static typing for a faulty lambda calculus. SIGPLAN Not., 41(9):38-49, 2006.
19. C. Wang, H.-S. Kim, Y. Wu, and V. Ying. Compiler-managed software-based redundant multi-threading for transient fault detection. In CGO '07: Proceedings of the International Symposium on Code Generation and Optimization, pages 244-258, Washington, DC, USA, 2007. IEEE Computer Society.
20. Y. Yeh. Triple-triple redundant 777 primary flight computer. In Proceedings of the 1996 IEEE Aerospace Applications Conference, volume 1, pages 293-307, February 1996.
21. Y. Yeh. Design considerations in Boeing 777 fly-by-wire computers. In Proceedings of the Third IEEE International High-Assurance Systems Engineering Symposium, pages 64 - 72, November 1998.