Design and hardware implementation of a chaotic encryption scheme for real-time embedded systems

2010 International Conference on Signal Processing and Communications, SPCOM 2010

Volumn , Issue , 2010, Pages

  Pande, Amit ^a   Zambreno, Joseph ^a  

^a Iowa State University   (United States)

Author keywords

Chaos; Encryption; FPGA implementation; Stream cipher

Indexed keywords

BIFURCATION DIAGRAM; CHAOS; CHAOTIC BEHAVIORS; CHAOTIC ENCRYPTIONS; CHAOTIC PROPERTIES; CHAOTIC STREAM CIPHER; CLOCK CYCLES; CLOCK FREQUENCY; EMBEDDED DEVICE; ENCRYPTED DATA; ENCRYPTION; FEEDBACK SCHEME; FPGA IMPLEMENTATIONS; FPGA TECHNOLOGY; HARDWARE IMPLEMENTATIONS; HARDWARE RESOURCES; HIGH POTENTIAL; LOGISTIC MAPS; MODIFIED LOGISTIC MAP; POWER CONSUMPTION; PSEUDORANDOM SEQUENCES; REAL-TIME EMBEDDED SYSTEMS; STABLE ORBIT; STREAM CIPHERS; TIME PARAMETER;

CHAOTIC SYSTEMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; EMBEDDED SYSTEMS; HARDWARE; HYDRAULICS; NETWORK SECURITY; REAL TIME SYSTEMS; SIGNAL PROCESSING;

CRYPTOGRAPHY;

EID: 77958468815     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPCOM.2010.5560478     Document Type: Conference Paper

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