Technology mapping and clustering for FPGA architectures with dual supply voltages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 11, 2010, Pages 1709-1722

  Chen, Deming ^a   Cong, Jason ^b   Dong, Chen ^a   He, Lei ^c   Li, Fei ^d   Peng, Chi Chen ^a  

^a University of Illinois at Urbana Champaign   (United States)

^b University of California   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d Actel Corp   (United States)

Author keywords

Dual supply voltages; field programmable gate array (FPGA); power optimization; technology mapping

Indexed keywords

DUAL SUPPLY VOLTAGES; DUAL-VDD; DYNAMIC POWER REDUCTION; FPGA ARCHITECTURES; LOW POWER; MAPPING ALGORITHMS; MAPPING PROCESS; POWER OPTIMIZATION; SUPPLY VOLTAGES; TECHNOLOGY MAPPING; TECHNOLOGY MAPPING ALGORITHMS; TOTAL POWER;

CONFORMAL MAPPING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; OPTIMIZATION; TECHNOLOGY;

CLUSTERING ALGORITHMS;

EID: 77958449776     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2061770     Document Type: Article

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