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Volumn 25, Issue 4, 2010, Pages 303-314

Compute unified device architecture (CUDA) based finite-difference time-domain (FDTD) implementation

Author keywords

Compute unified device architecture (CUDA); FDTD methods; Graphics processing unit (GPU) programming; Hardware accelerated computing; Parallel architectures

Indexed keywords

CELL MAPPING; CENTRAL PROCESSOR UNITS; COMPUTE UNIFIED DEVICE ARCHITECTURES; DEVELOPMENT ENVIRONMENT; FDTD METHOD; FDTD SIMULATIONS; FINITE DIFFERENCE TIME-DOMAIN; GPU COMPUTING; GRAPHICS CARD; GRAPHICS PROCESSING UNIT; GRAPHICS PROCESSING UNITS; HARDWARE ACCELERATED COMPUTING; HIGH PERFORMANCE SCIENTIFIC COMPUTING; SCIENTISTS AND ENGINEERS;

EID: 77958184943     PISSN: 10544887     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (43)

References (30)
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    • Inman, M.J.1    Elsherbeni, A.Z.2
  • 16
    • 59349098179 scopus 로고    scopus 로고
    • A GPU implementation of the 2D finite-difference time-domain code using high level shader language
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    • How to Render FDTD Computations More Effective Using a Graphics Accelerator
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    • Convolution PML (CPML): An Efficient FDTD implementation of the CFS-PML for arbitrary media
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    • Roden, J.A.1    Gedney, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.