Constructing short-length irregular LDPC codes with low error floor

IEEE Transactions on Communications

Volumn 58, Issue 10, 2010, Pages 2823-2834

  Zheng, Xia ^a,b,c   Lau, Francis C M ^a   Tse, Chi K ^a  

^a HONG KONG POLYTECHNIC UNIVERSITY   (Hong Kong)

^b Ericsson Ltd   (Hong Kong)

^c Ericsson Limited   (Macao)

Author keywords

Cycle indicator; distinguishable cycles; error floor; irregular LDPC codes; PEG ACSE algorithm; trapping set

Indexed keywords

CYCLE INDICATOR; DISTINGUISHABLE CYCLES; ERROR FLOOR; IRREGULAR LDPC CODES; PEG-ACSE ALGORITHM; TRAPPING SET;

ALGORITHMS; CODING ERRORS; FLOORS; FREQUENCY SELECTIVE FADING;

ERROR CORRECTION;

EID: 77958102413     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2010.083110.080638     Document Type: Article

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