Intel® QuickPath Interconnect architectural features supporting scalable system architectures

Proceedings - 18th IEEE Symposium on High Performance Interconnects, HOTI 2010

Volumn , Issue , 2010, Pages 1-6

  Ziakas, Dimitrios ^a   Baum, Allen ^a   Maddox, Robert A ^a   Safranek, Robert J ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Intel; Nehalem; QPI; QuickPath; Scalable; Xeon

Indexed keywords

ARCHITECTURE;

INTEL; NEHALEM; QUICKPATH; SCALABLE; XEON;

COMPUTER ARCHITECTURE;

EID: 77958092260     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HOTI.2010.24     Document Type: Conference Paper

References (7)

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2. G. Singh, R. A. Maddox, and R. J. Safranek, Weaving High Performance Multiprocessor Fabric. Architectural insights into the Intel QuickPath Interconnect. Intel Press, 2009
3. Intel, An Introduction to the Intel QuickPath Interconnect. Intel White Paper, January 2009
4. Intel, A Quantum Leap in Enterprise Computing, Unprecedented Reliability and Scalability in Multi-Processor Server, Product Brief, Intel 2010
5. M. Demshki, M. Kumar and R. Shiveley, Advanced Reliability for Intel® Xeon® Processor-based Servers, Intel White Paper, Version 1.0, March 2010
6. R. J. Chevance, Server Architectures: Multiprocessors, Clusters, Parallel Systems, Web Servers, and Storage Solutions. Elsevier Digital Press, December 2004
7. R. J. Safranek, Intel QuickPath Interconnect Overview, Proc. 21st Hot Chips Symposium on High Performance Chips., August 2009.